Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2000-05-01
2002-03-19
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S112000, C438S124000, C438S126000
Reexamination Certificate
active
06358780
ABSTRACT:
The present invention relates to the art of semiconductor chip packaging, and more specifically to semiconductor chip packages having moisture vents and to methods of making such assemblies.
Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits,” which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The interconnection between the chip itself and its supporting substrate is commonly referred to as a “first level” assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a “second level” interconnection.
The first level interconnection structures connecting a chip to a substrate are typically subject to substantial stresses caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperature of the chip and substrate rises each time the device is turned on and falls each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion, the chip and substrate ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress, which can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the chip and substrate are formed from like materials having similar coefficiency, of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
Certain designs have been directed to reducing problems associated with thermal cycling by redistributing the thermal cycling stress into a portion of the chip package itself. Such designs are shown in commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266 and 5,679,977, the disclosures of which are hereby incorporated by reference herein. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a compliant layer to reduce the CTE mismatch problems. Typically, the compliant layer includes an elastomeric layer which, in the finished package, is disposed between the chip carrier and the face surface of the chip. The compliant layer provides resiliency to the individual terminals, allowing each terminal to move in relation to its electrically connected chip contact to accommodate CTE mismatch as necessary during testing, final assembly and thermal cycling of the device.
Another problem with conventional epoxy-based (and other hydrophobic compounds) chip package assemblies includes moisture becoming entrapped within the package. Moisture can be introduced into the package through the printed circuit board or substrate, any encapsulant material and especially the adhesive used to attach the chip to the substrate. As a result, when a package having moisture trapped therein heats up during operation, the moisture is rapidly converted into a gas which expands dramatically. This rapid expansion of trapped gas typically causes the chip to delaminate from the substrate and adversely affects the electrical interconnections between the chip and the substrate. This phenomenon is referred to as the “popcorn” effect.
There have been a number of efforts directed to removing moisture trapped within chip packages. U. S. Pat. No. 4,866,506 to Nambu et al. discloses a flat plastic sealed lead frame package having an opening on an underside of the package which allows a die to be exposed to the atmosphere, thereby venting or releasing moisture from the package when the package is subjected to heat.
U. S. Pat. No. 5,296,738 to Freyman et al. discloses a printed circuit board substrate having at least one opening therein, the opening being located directed beneath a semiconductor chip so as to provide means for moisture relief when the chip package is subjected to extreme temperature variations. The opening in the printed circuit board substrate is initially covered on the back side of the printed circuit board with solder resist. The covered opening prevents the flow of die attach material from the top side surface through the opening and on to the back side solder pads. After final assembly of the package, the solder resist must be pierced or punctured to create the final opening for moisture relief.
U. S. Pat. No. 5,721,450 to Miles discloses another chip package having a moisture relief, including a semiconductor die having a top surface and a bottom surface and a substrate for receiving the semiconductor chip. The substrate has an aperture below the chip for providing moisture relief during temperature variations. An adhesive is disposed between the chip and the substrate for mounting the chip to the substrate. The chip is wirebonded to the substrate and an encapsulant for sealing the top surface of the chip is formed over the chip and portions of the substrate.
U.S. Pat. No. 5,557,150 to Variot et al. discloses a method for providing an overmolded semiconductor chip package which prevents delamination of the molding compound from the substrate by allowing the molding compound to flow through holes in the substrate and forming into it rivet-like anchors on the opposite side of the substrate.
Despite the above-mentioned solutions to moisture venting, still further improvements are necessary.
SUMMARY OF THE INVENTION
In one embodiment of the present invention a semiconductor chip package includes a semiconductor chip having surfaces and contacts and a layer of a moisture permeable material bonded to one surface of the chip. The package includes a moisture-impermeable encapsulant overlying the moisture-permeable layer and at least partially surrounding the chip. The moisture-permeable material typically includes a compliant layer, such as an elastomeric polymer or silicone. One such moisture-impermeable encapsulant material includes an epoxy or any other material which does not allow moisture to pass therethrough. The package has exposed exterior surfaces and terminals accessible at least one of the exposed exterior surfaces. The terminals are electrically connected to the contacts, such as by using flexible wire bonds. The moisture-permeable material preferably extends to at least one of the exposed exterior surfaces. In certain embodiments, the semiconductor chip has an upwardly-facing front surface with the contacts thereon and a back surface facing downwardly, with the moisture-permeable material extending beneath the back surface. The package has a downwardly-facing bottom surface and the terminals are being accessible beneath the moisture-permeable material for being connected at the bottom surface of the package. The package preferably includes a rigid or flexible circuit board at the bottom surface thereof, whereby the moisture-permeable material is disposed between the circuit board and the moisture-impermeable material.
In certain embodiments, the package has edge surfaces and the moisture-permeable material extends to at least one of the edge surfaces so that any moisture entrapped within the package is vented through the edge surfaces. In certain embodiments the moisture-permeable material has a non-uniform thickness. For example, the moisture-permeable material may have a substantially flat central region with the chip overlying the central region, and a peripheral region at the package edge surface. The peripheral region at the package edge surface extends upwardly from the circuit board so that the peripheral region of the moisture-permeable material is thicker than the central region.
In certain
Pickett Christopher M.
Smith John W.
Lerner David Littenberg Krumholz & Mentlik LLP
Picardat Kevin M.
Tessera Inc.
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