Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-11-16
2002-09-17
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S760000, C257S700000, C257S701000, C257S774000, C257S643000, C257S642000, C257S748000, C257S750000, C257S003000
Reexamination Certificate
active
06452274
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a low dielectric layer as an inter-layer insulating layer and method of manufacturing a semiconductor device having that structure, more particularly relates to technology for formation of multilayer interconnections able to be used for under 0.25 &mgr;m rule device processes.
2. Description of the Related Art
Recently, increasingly fine interconnections and reduced interconnection pitches have been demanded along with the increasing miniaturization of semiconductor devices. Further, increasingly lower dielectric rates have been demanded for inter-layer insulating layers along with demands for lower power consumption and higher speeds. In particular, in logic type devices, a rise in resistance due to finer interconnections and an increase in the capacitance of the interconnections leads to a reduction in the speed of the device, so finer multilayer interconnections having low dielectric layers as inter-layer insulating layers have become essential.
Increasing finer interconnection widths and reduced pitches, however, not only increase the ratio of the length and width of the interconnections themselves, but also increase the aspect ratio of the spaces between the interconnections and, as a result, place an additional burden on the formation of longitudinally narrow, fine interconnections, the burying of the fine spaces between interconnections by inter-layer layers, etc. and therefore both complicate the process and increase the number of process steps.
To solve this problem, there is known the so-called “damascene” process of simultaneously burying the contact holes and interconnection grooves by aluminum reflow sputtering and then smoothing the surface aluminum by chemical mechanical smoothing (CMP).
The damascene process does not require the forming of high aspect ratio aluminum interconnections by etching or burying of the narrow spaces between interconnections by an inter-layer insulating layer, so can greatly reduce the number of process steps. In this process, the higher the aspect ratio of interconnections and the greater the total number of interconnections, the greater the contribution to the reduction of the total cost. Further, reduction of the dielectric rate of the inter-layer insulating film can be expected to reduce the capacitance of the space between interconnections.
However, films comprised of materials with small dielectric constants differ tremendously in nature from the silicon oxide films used in conventional devices. No process technology has yet been developed for them. Therefore, practical technology for this is now being sought.
Further, in recent years, use of xerogel as a material in semiconductor devices is being closely examined as it promises a dielectric constant of less than 2.0.
In relation to this art, Japanese Unexamined Patent Publication (Kokai) No. 8-70005 discloses a structure, as shown in
FIG. 9
, providing dummy leads
93
for dispersing heat in a low dielectric material
96
as a method of increasing the reliability of metal leads
94
. This structure is comprised of a substrate
92
on which are provided metal leads
94
made of an aluminum alloy etc., a low dielectric material
96
comprised of a space, silica-airogel, organic SOG, fluorine doped silicon oxide, etc. at least between the metal leads
94
, a heat conductive insulating layer
97
comprised of a laminate of AlN, Si
3
N4
4
, and AlN deposited on the metal leads
94
and the low dielectric material
96
, and dummy leads
93
comprised of an aluminum alloy etc. adjacent to the metallic leads
94
.
In this structure, the heat from the metal leads
94
can move to the dummy leads
93
which are able to disperse the heat and to the heat conductive insulating layer
97
which is made of an insulating material such as AlN having a heat conductivity 20% higher than the low dielectric material, preferably a heat conductivity 20% higher than that of Si
3
N
4
. By structuring the device in this way, it is possible to reduced the interconnection capacitance between lines (or leads) and, along with the fall in the heat conductivity of the low dielectric material, prevent damage to the metal leads by the Joule's heat effect, which becomes a problem when using metal leads with a high aspect ratio, and thereby obtain a semiconductor device having more reliable metal leads.
Turning now to the problems to be solved by the present invention, the above-mentioned damascene method forms the interconnection layer in advance on the inter-layer insulating layer, then buries this with a metal and polishes the metal by CMP to form the interconnections. With conventional inter-layer insulating layers, use has been made of an inorganic material such as a silicon oxide film. Use is now however being made of materials with low dielectric rates with the object of suppressing an increase in capacitance along with miniaturization. Most materials with low dielectric rates are organic. Organic films have a hardness of {fraction (1/10)} to {fraction (1/100)} that of the conventional silicon oxide and other inorganic films and therefore lack the hardness required for the damascene process.
That is, most substances with low dielectric constants, in particular low dielectric films with dielectric constants less than 3, are also organic. Organic films are softer than the silicon oxide films used for conventional inter-layer insulating layers. For example, compared by Young's modules, a silicon oxide has a value of 5×10
10
, while a resin used for an organic film has a small value of 0.3 to 0.8×10
10
.
Therefore, when forming interconnections by the damascene method, many scratches are formed on the organic film. These scratches cause lower product yield. Therefore, the general practice has been to form a silicon oxide layer or nitride layer on the organic film, but these layers have a higher dielectric rate than the organic film, so there was the problem that the capacitance between interconnections ended up increasing.
Therefore, the idea has been proposed of making joint use of a silicon oxide film and a silicon nitride film at the time of the damascene process. These films, however, have high dielectric rates and therefore had the problem of halving the effect of reduction of the dielectric rate by the organic film.
Further, an organic film has a very small heat conductivity of about {fraction (1/10)} that of the inter-layer insulating layer (silicon oxide layer) used for conventional semiconductor devices and therefore had a serious effect on the dispersion of the heat of the elements. That is, while the amount of heat generated per unit area falls along with the reduction in size of a device, the heat conductivity of the paths for radiation of that heat has been falling as well.
Therefore, a structure of a device giving due consideration to the paths for heat dispersion is desired.
Xerogel is a well-known substance, for example, used as a desiccant under the name of “silica gel”. Use for a semiconductor device however would be difficult as things now stand due to the various requirements on reliability. That is, xerogel is comprised of 50% to 90% by volume and therefore suffers from problems in mechanical strength, heat conductivity, heat resistance, moisture resistance, inter-layer adhesion, etc.
Accordingly, a structure of a device which solves the above mentioned problem and enables use of xerogel with its low dielectric constant is desired.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device using a low dielectric film as an inter-layer insulating layer and a method of manufacturing the same.
The present inventors, in consideration of the above problems, invented a semiconductor device having an organic layer as a low dielectric layer or an organic layer containing xerogel as an inter-layer insulating layer and formed by the damascene method and a method of manufacturing the same.
That is, according to the present inv
Hasegawa Toshiaki
Nakayama Hajime
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Williams Alexander O.
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