Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-04-28
2002-05-07
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S067000, C438S107000, C438S116000, C438S296000, C438S361000, C438S424000, C438S427000, C438S430000
Reexamination Certificate
active
06383837
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a multi-chip semiconductor device and a chip to be applied to this device and, more particularly, to a multi-chip semiconductor device effective to improve alignment and a chip to be applied to this device.
This application is based on Japanese Patent Application No. 9-109130, filed on Apr. 25, 1997, the content of which is incorporated herein by reference.
Recently, a very large scale integrated circuit (chip) manufactured by integrally forming a number of elements such as transistors and resistors on a semiconductor substrate is often used in an important portion of a computer or a communication apparatus. The performance of this chip is closely related to the performance of a whole apparatus. On the other hand, a so-called multi-chip semiconductor module has been proposed in which a plurality of chips are stacked to improve the performance of a whole apparatus. Recently, the assignee of the present application has proposed a multi-chip semiconductor device chip, three or more of which can be connected in a small space by a simple method, and a method of forming the chip (U.S. Pat. application Ser. No. 08/980,873 filed on Dec. 1, 1997, now abandoned in favor of a continuation-in-part U.S. patent application Ser. No. 09/377,486 filed on Aug. 20, 1999).
One characteristic feature of this chip is that a through hole is formed in a semiconductor device on which elements are integrally formed and a connecting plug made of a conductive material is formed in this through hole. Chips are electrically connected via these connecting plugs to accomplish a multi-chip semiconductor device including a plurality of stacked chips.
In this multi-chip semiconductor device, pads made of a conductive material are used to connect connecting plugs of different chips or to electrically connect connecting plugs of different chips and a multilevel is interconnecting layer. This pad has a solder bump.
When misalignment between chips is taken into consideration, it is necessary to form a pad having a relatively large area. This is so because the solder bump described above and a connecting plug to be connected to this solder bump are not connected in some cases due to misalignment between the chips. However, forming such pads having a large area is contrary to demanding improved performance by forming pads as many as possible in a chip in order to reduce the parasitic resistance in the interconnecting layer.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multi-chip semiconductor device by which high-accuracy alignment is possible and a chip to be applied to this device.
It is a second object of the present invention to provide a method and an apparatus for manufacturing the multi-chip semiconductor device.
It is a third object of the present invention to provide a method of manufacturing a chip to be applied to the multi-chip semiconductor device, and a method of aligning the chips.
According to an aspect of the present invention, there is provided a chip applied to a multi-chip semiconductor device, comprising: a semiconductor substrate on which at least one element is formed; a connecting portion formed in the semiconductor substrate and electrically connected to another chip; and two or more light-transmitting portions formed in the semiconductor substrate.
According to the second aspect of the present invention, there is provided a method of manufacturing a chip applied to a multi-chip semiconductor device, comprising the steps of: forming a plurality of holes having a desired depth in a surface of a semiconductor substrate; forming an insulating film on side walls and bottoms of the holes; burying a conductive material in the holes except for at least two holes; and exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed.
According to the third aspect of the present invention, there is provided a method of aligning a plurality of stacked chips each having a light-transmitting portion, comprising the steps of:
irradiating light onto one of uppermost and lowermost chips of the stacked chips; detecting light output from the stacked chips through the light-transmitting portions of the chips; and aligning the chips in accordance with the detected light.
According to the fourth aspect of the present invention, there is provided a multi-chip semiconductor device comprising: a plurality of stacked chips; and a plurality of conducting portions each formed between the chips, wherein each of the chips comprises: a semiconductor substrate on which at least one element is formed; a connecting portion formed to extend through the semiconductor substrate and electrically connected to an adjacent chip via the conducting portions arranged on both surfaces of the semiconductor substrate; and two or more light-transmitting portions formed in the semiconductor substrate.
According to the fifth aspect of the present invention, there is provided a method of manufacturing a multi-chip semiconductor device, comprising the steps of: manufacturing a plurality of semiconductor substrates; stacking the semiconductor substrates; arranging a plurality of conducting portions between the semiconductor substrates; aligning the semiconductor substrates; and electrically connecting the semiconductor substrates, wherein the step of manufacturing the semiconductor substrates comprises the substeps of: forming a plurality of holes having a desired depth in a surface of a semiconductor substrate; forming an insulating film on side walls and bottoms of the holes; burying a conductive material in the holes except for two holes; and exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed, and the step of performing alignment comprises the substeps of: irradiating light onto one of uppermost and lowermost semiconductor substrates of the stacked semiconductor substrates; detecting light output from the stacked semiconductor substrates through holes except for the holes formed in the semiconductor substrates and filled with the conductive material; and aligning the semiconductor substrates in accordance with the detected light.
According to the sixth aspect of the present invention, there is provided an apparatus for manufacturing a multi-chip semiconductor device, comprising: a holding mechanism for stacking and holding a plurality of semiconductor substrates each having a light-transmitting portion in a predetermined position; a coarse adjustment unit for coarsely moving each of the semiconductor substrates; a fine adjustment unit for finely moving each of the semiconductor substrates; a light source for irradiating light onto one of uppermost and lowermost semiconductor substrates of the semiconductor substrates; a light-receiving unit for detecting light output from the stacked semiconductor substrates through the light-transmitting portions formed in the semiconductor substrates; and a controller for controlling the coarse adjustment unit and the fine adjustment unit in accordance with an amount of the light detected by the light-receiving unit, thereby aligning the semiconductor substrates.
In the present invention as described above, high-accuracy alignment can be performed by using multi-chip semiconductor device chips having light-transmitting portions (hollow portions) for alignment.
This obviates the need for forming pads having a relatively large area by taking account of misalignment, unlike in conventional structures. Consequently, it is possible to form a large number of pads in a chip and reduce the parasitic resistance in the interconnecting layer.
Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention may be realized and obtained by means of the instrumentalities and combinatio
Diaz José R.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Eddie
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