Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-07-16
2002-03-12
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S258000
Reexamination Certificate
active
06356152
ABSTRACT:
FIELD OF INVENTION
This invention relates generally to electronic amplifiers and more particularly to CMOS fixed gain amplifiers.
BACKGROUND OF THE INVENTION
Amplifiers are commonly used in electronic applications. One example of the use of an amplifier is in a disk storage system commonly used in personal computers known as hard disk drives, HDD. U.S. Pat. No. 5,831,888 entitled “Automatic Gain Control Circuit” and assigned to Texas Instruments Incorporated, the assignee of the present invention, sets forth generally the description of disk storage. The HDD device generally includes a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a preamplifier, a read channel, a write channel, a servocontroller, a memory and control circuitry to control the operation of the HDD and to properly interface the HDD to a host or system bus. The following U.S. Patents describe various aspects of HDD devices:
5,535,067
Frequency Controlled Reference Generator Issued
07/09/96
5,570,241
Single Channel, Multiple Head Servo . . .
10/29/96
5,862,005
Synchronous Detection Of Wide BI-Phase . . .
01/19/99
5,793,559
In Drive Correction Of Servo Pattern . . .
08/11/98
5,719,719
Magnetic Disk Drive With Sensing . . .
02/17/98
5,444,583
Disk Drive Having On-Board Triggered . . .
08/22/95
5,448,433
Disk Drive Information Storage Device . . .
09/05/95
5,208,556
Phase Lock Loop For Sector Servo System
05/04/93
5,642,244
Method and Apparatus For Switching . . .
06/24/97
Prior art
FIG. 1
illustrates a partial HDD system. A disk/head assembly
12
stores data. A magnetoresistive, MR, head
14
works through magnetic media to read data from disk
12
or to write data to disk
12
. A write occurs through an inductive element in the MR head to the magnetic media disk assembly
12
and a read occurs by sensing the magnetic shifts in the disk assembly
12
by using the resistive read element of the MR head
14
. A preamplifier
16
, typically of the single ended variety, connects to MR head
14
to provide an initial amplification stage. The output of the preamplifier
16
is an analog signal which flows to a read channel
18
for further processing.
The read channel
18
in prior art
FIG. 1
takes the analog signal from preamplifier
16
and conditions it to provide a digital output signal that will be sent by an appropriate bus structure to other components of a computer system, such as, for example, the digital signal processor in either the modem or the graphics card. An automatic gain control circuit
18
a
is the first part of the read channel
18
. It provides an output signal having a larger amplitude than the input from preamplifier
16
. A low pass filter
18
b
receives the amplified read signal and removes undesirable noise, such as high frequency noise, and generates a filtered read signal that is input to a fixed gain amplifier
18
c.
The output signal of the low pass filter
18
b
is typically a fairly large voltage input of around a 0.4 volt peak to peak differential. From there, the signal flows into a fixed gain amplifier, FGA,
18
c.
The fixed gain amplifier
18
c
provides sufficient amplification to the output of the low pass filter
18
b
to allow sample space processor
18
d
and digital processor
18
e
to perform the analog to digital conversion of the read signal.
There are several requirements that govern the design of fixed gain amplifier
18
c.
Power supply voltages are continually decreasing and are typically below 2.9 volts, at present, in CMOS applications. Given the low power supply, a CMOS amplifier still needs to have a really wide linear range and be fast enough to support the data rate at which the channel operates. The frequency range of the HDD is up to around 300 megahertz, at present. The output signal of low pass filter
18
b,
being about 0.4 volt peak to peak differential, is a very high input to the FGA
18
c.
If FGA
18
c
were just a regular differential pair, it would have a linear range of only about 26 millivolts which is very tiny. Additionally, one thing the FGA
18
c
should not do is to ruin what was done in the AGC
18
a
and the LPF
18
b.
So the total harmonic distortion, THD, should be very low, yet both the gain and a high bandwidth must be preserved. Additionally, the FGA
18
c
should provide a reasonable amount of amplification (typically around 4 V/V) and be manufacturable. That is, when built on silicon, it must be easy to match and be flexible.
Prior art
FIG. 2
illustrates a fixed gain amplifier typical of the type used for FGA
18
c.
FGA
18
c
has two main parts: an amplifier core
20
; and a common mode feedback circuit
22
. In the amplifier core
20
, the resistor RE
1
is typically referred to as emitter degeneration resistor. Input transistors M
1
and M
2
are CMOS source followers. They follow the input voltage appearing at inputs Vin and VinB. Resistors RL
1
and RL
2
are the load resistors. Transistors M
5
and M
6
are cascoded devices. Transistor M
5
and current source I
5
form a cascoded mirror that is a high swing cascoded mirror. [In integrated circuit structures, when one device is connected on top of another device, (current source I
5
is actually a MOS transistor in a silicon implementation) the structure is referred to as a cascoded stage.] Output transistors M
5
and M
6
are cascoded transistors that actually shield the mirroring transistors I
5
and I
6
(shown as ideal sources) so that the voltages on node
5
and node
6
don't vary too much.
The common mode feedback circuit
22
of prior art
FIG. 2
, as the name implies, provides a mechanism to control the common mode voltage. It helps keep the dc values of the output nodes Vout and VoutB at a desired value independent of the variations in the manufacturing process and the fluctuations in the operating conditions. The common mode needs to be controllable because the next stage, the sample space processor
18
d,
can operate correctly only for a very narrow range of input common mode voltages. A very simple amplifier compares the reference common mode to the actual extracted common mode at the output. The circuit thus compares the common mode voltage to the average voltage at Vout and VoutB to see what the dc value of the output is. If the value is larger than the common mode, it needs to be brought down. If the value is smaller than the common mode, it needs to be brought up. The circuit folds transistors M
9
and M
10
into amplifier
20
and injects current on nodes N
5
and N
6
in order to affect the total DC current going through the load resistors RL
1
and RL
2
and consequently set the correct output common mode.
In prior art
FIG. 2
, the degeneration resistor RE
1
on the input stage of the amplifier allows for a larger input voltage with a larger input voltage swing. By adding the degeneration resistor, the linear range of the amplifier is improved. The differential current that goes through the input source followers M
1
and M
2
is defined by the size of the resistor RE
1
and the swing of the differential input voltage. With appropriate sizing of resistor RE
1
the differential current going through M
1
and M
2
can be made reasonably smaller than the DC current going through M
1
and M
2
, hence improving the linear range and reducing the overall distortion of the output signal. However, what brings in the majority of distortion to the amplifier is that the total currents through M
1
and M
2
are not independent of the input signal. In other words, the voltage gain across M
1
and M
2
instead of being constant is directly modulated by the variation in the input signal causing distortions in the output signal. The prior art circuit thus has gain dependant on the amplitude of the differential input signal making it unsuitable for very low distortion applications.
U.S. Pat. No. 5,142,242 to Schaffer, issued Aug. 25, 1992, provides a method of making the gain of the input transistors less dependant on the variation in the input signal. In the CMOS embodiment disclosed
Bloodworth Bryan E.
Jezdic Andrija
Wallberg John L.
Brady III W. James
Hernandez Pedro P.
Nguyen Khanh Van
Pascal Robert
Telecky , Jr. Frederick J.
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