Delay circuit

Details Delay circuit Delay circuit

2001-03-06

2002-09-10

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S285000, C327S271000, C327S398000

Reexamination Certificate

active

06448833

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay circuit using MOS capacitors, and more particularly to a delay circuit formed within a semiconductor integrated circuit and capable of obtaining a stable delay effect even when signal voltage varies.
2. Description of the Related Art
Conventionally, when clock centering adjustment or signal timing adjustment is performed in a wafer test step or a test step after assembly for a semiconductor integrated circuit, a MOS transistor for load capacitance is mainly used as a delay circuit. For example, a circuit used as the delay circuit is formed such that gates of a P-type MOS transistor for load capacitance and an N-type MOS transistor for load capacitance are connected to a clock line or a signal line, supply voltage V
DD
is applied to a terminal at which a source and a drain are joined together (hereinafter referred to as “source-drain”) of the P-type MOS transistor for load capacitance and ground voltage V
GND
is applied to a source-drain of the N-type MOS transistor for load capacitance. When a signal with an appropriate voltage is input to the signal line of this circuit, the MOS transistors act as capacitors which cause the signal current to be charged in the MOS transistors for load capacitance and thus to be outputted with a certain delay after the input.
FIG. 1
shows an example of a conventional delay circuit. Signal line
10
is connected to a gate of P-type MOS transistor
3
for load capacitance and to a gate of N-type MOS transistor
4
for load capacitance. Source-drains of these MOS transistors
3
and
4
are connected to output terminals of CMOS inverters
5
and
6
, respectively. In each of CMOS inverters
5
and
6
, supply voltage V
DD
is applied to a source of a P-type MOS transistor, while ground voltage V
GND
is applied to a drain of an N-type MOS transistor. Fuse or resistor
8
is connected to an input terminal of CMOS inverter
5
. Output terminal of inverter
7
is connected to input terminal of CMOS inverter
6
, while input terminal of inverter
7
is connected to a fuse or resistor
8
.
In the aforementioned circuit, switching of the fuse or resistor
8
enables selection of voltages applied to the source-drains of MOS transistors
3
and
4
for load capacitance through inverters
5
and
6
. When certain voltages are applied to the source-drains of MOS transistors
3
and
4
for load capacitance, MOS transistors
3
and
4
for load capacitance act as capacitances in accordance with the voltage of a signal on signal line
10
to produce a delay effect for the signal.
The aforementioned delay circuit, however, has a problem of a narrow range of signal voltages in which stable load capacitances can be obtained. Such a tendency is significant especially when the supply voltage is low. More detailed description is hereinafter made with reference to FIG.
1
. When fuse or resistor
8
is at a low level, the voltage at the input terminal of inverter
5
is at a low level, the P-type MOS transistor in inverter
5
is turned ON, and the N-type MOS transistor is turned OFF. Thus, the voltage at the source-drain of P-type MOS transistor
3
for load capacitance is at V
DD
. Since a signal through fuse or resistor
8
is reversed at inverter
7
, a signal at a high level is input to the input terminal of inverter
6
. Therefore, the P-type MOS transistor in inverter
6
is turned OFF and the N-type MOS transistor is turned ON, and thus the voltage at the source-drain of N-type MOS transistor
4
for load capacitance is at V
GND
.
When a threshold voltage of the P-type MOS transistor is V
tp
and a threshold voltage of the N-type MOS transistor is V
tn
, a gate voltage for allowing P-type MOS transistor
3
for load capacitance to have a load capacitance is equal to or lower than the voltage represented by V
DD
−V
tp
, while a gate voltage for allowing N-type MOS transistor
4
for load capacitance to have a load capacitance is equal to or higher than the voltage represented by V
GND
+V
tn
.
FIG. 2
shows ranges of gate voltages allowing to have load capacitances: range
23
for allowing P-type MOS transistor
3
for load capacitance, range
21
for N-type MOS transistor for load capacitance and range
22
effective for both P-type MOS transistor
3
and N-type MOS transistor
4
for load capacitance. Gate voltages range
22
in which both P-type MOS transistor
3
for load capacitance and N-type MOS transistor
4
for load capacitance have a load capacitance is from V
GND
+V
tn
to V
DD
−V
tp
. The range is narrower than the range of signal voltages when the latter extends from V
GND
to V
DD
. For this reason, a change in signal voltage may cause the inability to obtain a stable load capacitance value, leading to an unstable delay effect. Particularly, when the difference between the supply voltage and the ground voltage is smaller, the range of gate voltages in which both P-type MOS transistor
3
for load capacitance and N-type MOS transistor
4
for load capacitance have a load capacitance is further narrowed to present a more unstable delay effect.
SUMMARY OF THE INVENTION
The present invention has been made in view of such a problem, and it is an object thereof to provide a delay circuit which produces a stable delay effect even with changes in signal voltage.
A delay circuit according to a first aspect of the present invention comprises a P-type MOS transistor for load capacitance whose gate is connected to a signal line and source and drain are connected to each other to make a source-drain, an N-type MOS transistor for load capacitance whose gate is connected to the signal line and source and drain are connected to each other to make a source-drain, first power supply means for applying a boosted voltage higher than supply voltage V
DD
to a source-drain of the P-type MOS transistor for load capacitance, and second power supply means for applying a substrate voltage lower than ground voltage V
GND
to a source-drain of the N-type MOS transistor for load capacitance.
In this case, it is preferable that the delay circuit further comprises means for switching between the boosted voltage higher than supply voltage V
DD
and a voltage equal to or lower than ground voltage V
GND
as a voltage applied by the first power supply means to the source-drain of the P-type MOS transistor for load capacitance, and means for switching between a voltage equal to or higher than supply voltage V
DD
and the substrate voltage lower than ground voltage V
GND
as a voltage applied by the second power supply means to the source-drain of the N-type MOS transistor for load capacitance.
A delay circuit according to a second aspect of the present invention comprises a P-type MOS transistor for load capacitance whose gate is connected to a signal line and source and drain are connected to each other to make a source-drain, an N-type MOS transistor for load capacitance whose gate is connected to the signal line and source and drain are connected to each other to make a source-drain, a first CMOS inverter having an output terminal connected to a source-drain of the P-type MOS transistor for load capacitance, first power supply means for applying a boosted voltage higher than supply voltage V
DD
to a higher potential side of the first CMOS inverter and for applying a voltage equal to or lower than ground voltage V
GND
to a lower potential side of the first CMOS inverter, a second CMOS inverter having an output terminal connected to a source-drain of the N-type MOS transistor for load capacitance, second power supply means for applying a voltage equal to or higher than supply voltage V
DD
to a higher potential side of the second CMOS inverter and for applying a substrate voltage lower than ground voltage V
GND
to a lower potential side of the second CMOS inverter, and switching means for applying a voltage for controlling the operations of the first and second CMOS inverters to the first and second CMOS inverters to switch between the voltage on the higher

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