Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-08-09
2002-09-03
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S532000, C257S533000, C257S536000
Reexamination Certificate
active
06445055
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and in particular to a technique that is effectively applicable to a high withstand voltage LSI (Large Scale Integrated Circuit) formed on a SOI (Silicon on Insulator) substrate.
The SOI substrate means a substrate having a silicon film formed on an insulating film. A high withstand voltage LSI such as a communication LSI or the like includes a plurality of semiconductor elements formed on the SOI substrate.
Furthermore, this plurality of semiconductor elements are formed on an island region separated by trenches in which an insulating film is embedded
For example, Japanese Patent Laid-open No. 11-317445 discloses such a semiconductor device that a circuit region is surrounded several times over by a trench insulating film to achieve a high withstand voltage characteristic.
In this way, it is possible to achieve increase in the withstand voltage by covering the above-mentioned island region with trenches several times over.
SUMMARY OF THE INVENTION
However, as described later, the present inventors have recognized that there is a limit in increasing the withstand voltage by using such the method.
An object of the present invention relating to a semiconductor integrated circuit device and a manufacturing method thereof is to provide a semiconductor integrated circuit device having a high withstand voltage and a manufacturing method of the same.
Another object of the present invention is to provide a semiconductor integrated circuit device having a high withstand voltage and a manufacturing method of the same and thereby improve the reliability of the semiconductor integrated circuit device.
The above-mentioned objects and novel features of the present invention will become apparent to description of the present specification and accompanying drawings.
Of inventions disclosed in the present application, representative inventions will be briefly described as follows.
A semiconductor integrated circuit device according to the present invention has a first and second circuit regions on a main surface of an SOI substrate and includes a first insulating isolation trench surrounding said first circuit region, a second insulating isolation trench surrounding this first insulating isolation trench, a third insulating isolation trench surrounding said second circuit region, and a fourth insulating isolation trench surrounding this third insulating isolation trench, and the first circuit region and a first isolating region defined by said first and second insulating isolation trenches are connected by a wiring resistor or a diffused resistor in the SOI substrate. Said first isolating region and an intermediate region extending between said second and fourth insulating isolation trenches are connected via a wiring resistor or a diffused resistor in the SOI substrate. Furthermore, said second circuit region and a second isolating region defined by said third and fourth insulating isolation trenches are connected via a wiring resistor or a diffused resistor in the SOI substrate, and the second isolating region and the intermediate region are connected via a wiring resistor or a diffused resistor in the SOI substrate.
According to the above-mentioned means, since the voltage generated by the wiring resistors or the diffused resistors is distributed, each voltage applied to the insulating isolation trenches can be made uniform. Therefore, the withstand voltage of the first and second circuit regions can be increased.
Furthermore, if said first and second circuit regions are surrounded by wide insulating isolation trenches, the withstand voltage of the first and second circuit regions can be increased.
Furthermore, if said first and second circuit regions are connected via a capacitance element, it is possible to transmit only electric signals during maintenance of the insulation states of the first and second circuit regions.
A manufacturing method of a semiconductor integrated circuit device according to the present invention comprises the steps of: etching a semiconductor region constituting an SOI substrate until an insulating layer is exposed, and thereby forming a first isolation groove surrounding a first circuit region on the semiconductor region, a second isolation groove surrounding said first isolation groove, a third isolation groove surrounding a second circuit region, and a fourth isolation groove surrounding said third isolation groove; depositing a silicon oxide film on the semiconductor region in addition to insides of said first to fourth isolation grooves; removing the silicon oxide film located outside the first to fourth isolation grooves, and thereby forming a first to fourth insulating isolation trenches formed of the silicon oxide film embedded in said first to fourth isolation grooves; forming respectively a first to fourth wiring resistors on the first to fourth insulating isolation trenches; and forming a wiring for connecting, via the first to fourth wiring resistors, both said first or second circuit region and an intermediate region located between said second and fourth insulating isolation trenches.
Furthermore, a manufacturing method of a semiconductor integrated circuit device according to the present invention further comprises a step of forming a stopper film on a silicon oxide film located on each of said isolation grooves.
According to the above-mentioned means, it is possible to form a semiconductor integrated circuit device having a high withstand voltage.
REFERENCES:
patent: 5747867 (1998-05-01), Oppermann
patent: 5977606 (1999-11-01), Sakurai et al.
patent: 6376296 (2002-04-01), Tung
patent: 11-317445 (1999-11-01), None
Horiuchi Mitsuaki
Iwasakii Takayuki
Kojima Yasuyuki
Nemoto Minehiro
Sakai Koki
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Ngo Ngan V.
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