Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-02-25
2002-04-23
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S715000, C438S724000
Reexamination Certificate
active
06376386
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of etching a silicon nitride layer and a method of manufacturing a semiconductor device including a step of patterning the silicon nitride layer.
2. Description of the Prior Art
With the development of miniaturization of the semiconductor integrated circuit (LSI), a SAC (Self Alignment Contact) technique and a BLC (Border Less Contact) technique have been employed to arrange the wirings from an impurity diffusion layer to a field insulating film.
According to the SAC technique, in the event that wirings are connected to two MOS transistors which employ one impurity diffusion layer as a common constituent element and the wirings are to be connected to a common impurity diffusion layer between two gate electrodes, connecting positions of the wirings are regulated by an insulating layer formed on surfaces of two gate electrodes.
Like the above, with the use of the SAC technique, the wirings can be easily and firmly connected to the impurity diffusion layer between the gate electrodes which are narrowed together with the miniaturization.
According to the BLC technique, grooves are formed in a device isolation region of a semiconductor substrate, then silicon oxide is filled in the grooves, then an impurity diffusion layer is formed on a semiconductor substrate, then wirings are formed in a region spreading from the impurity diffusion layer to the device isolation region.
If such BLC technique is employed, an alignment margin in the contact area between the wiring and the impurity diffusion layer can be increased.
Next, examples of the semiconductor device employing the SAC technique and the BLC technique in the prior art will be explained hereunder.
SAC technique
As shown in
FIG. 17A
, a gate electrode
103
is formed on a silicon substrate
100
via a gate insulating layer
102
and then a cap layer
104
made of SiO
2
is formed on the gate electrode
103
. Side walls
105
made of SiO
2
are formed on the side surfaces of the gate electrode
103
. Impurity diffusion layers
101
on the silicon substrate
100
are formed by a first ion implantation with low concentration after the gate electrodes
103
have been formed and a second ion implantation with high concentration after the side walls
105
are formed to have an LDD (Lightly Doped Drain) structure.
In such condition, after a thin protection film
106
made of SiO
2
is formed on an overall surface, a covering layer
107
made of Si
3
N
4
is formed and then an interlayer insulating layer
108
made of BPSG and an intermediate layer
109
made of SiO
2
are formed on the covering layer
107
.
Subsequently, in order to form contact holes in the interlayer insulating layer
108
and the intermediate layer
109
, a photoresist
110
having windows
111
over gaps between the side walls
105
is formed.
In turn, as shown in
FIG. 17B
, contact holes
112
are formed by dry-etching the interlayer insulating layer
108
via the windows
111
of the photoresist
110
in the vertical direction. In this case, the covering layer
107
made of Si
3
N
4
having a small etching rate may be used as an etchant to etch the interlayer insulating layer
108
and the intermediate layer
109
. Hence, the cap layer
104
and the side walls
105
still remain beneath the covering layer
107
because the covering layer
107
serves as an etching stopper.
Next, as shown in
FIG. 17C
, the covering layer
107
and the protection film
106
formed beneath the contact holes
112
are removed by etching. Thus, the impurity diffusion layers
101
are formed on the side surfaces of the side walls
105
are exposed. As the method of etching the covering layer
107
made of Si
3
N
4
, reactive ion etching using the fluorine gas can be employed. In addition, etching of the protection film
106
made of SiO
2
is executed by use of dilution hydrogen fluoride.
After the photoresist
110
has been removed, wirings are formed on the interlayer insulating layer
108
, though not particularly depicted, and then the wirings are connected to the impurity diffusion layers
101
via clearances between the contact holes
112
and clearances between the side walls
105
.
BLC technique
First, steps of forming up to a structure shown in
FIG. 18A
will be explained.
A groove
112
is formed is formed in the device isolation region of the silicon substrate
121
, and then a buried insulating film
123
made of silicon oxide is filled into the groove
122
. As a method of filling the buried insulating film
123
into the groove
122
, such a method can be employed, for example, that the buried insulating film
123
is formed by CVD (Chemical Vapor Deposition) in the groove
122
and on the silicon substrate
121
and then the buried insulating film
123
on a surface of the silicon substrate
121
is removed by polishing.
A gate insulating film
124
, a gate electrode
125
, and a gate covering insulating film
126
are then formed in an active region. Then, low-impurity concentration regions
127
a
,
127
d
are formed by ion-implanting the impurity into the silicon substrate
121
on both sides of the gate electrode
125
at a low dosage by use of the gate electrode
125
as a mask.
Then, an insulating film
128
made of silicon nitride and silicon nitride oxide is formed on the silicon substrate
121
, the gate covering insulating film
126
, and the low-impurity concentration regions
127
a
,
127
d.
Thereafter, as shown in
FIG. 18B
, the insulating film
128
is etched in the substantially vertical direction by RIE (Reactive Ion Etching) such that the insulating film
128
remains on side surfaces of the gate electrode
125
and the gate covering insulating film
126
. Such insulating films
128
remaining on the side surfaces of the gate electrode
125
are called side walls.
Then, as shown in
FIG. 18C
, using the side walls
128
and the gate covering insulating film
126
as a mask, impurity is ion-implanted at a high dosage into the active region which is not covered with the gate electrode
125
and the side walls
128
. Therefore, high-impurity concentration regions
129
a
,
129
d
are formed in the active region.
The LDD structure impurity diffusion layers
129
a
,
129
d
can be formed on both sides of the gate electrode
125
by the high-impurity concentration regions
129
s
,
129
d
and the low-impurity concentration regions
127
a
,
127
d.
As shown in
FIG. 18D
, silicide layers
131
s
,
131
d
are formed on surfaces of the low-impurity concentration regions
127
s
,
127
d
by the salicide (self-align silicide) technique.
Thus, a MOS transistor can be formed in the active region.
After this, as shown in
FIG. 18E
, a silicon nitride film
132
is formed in the active region and the device isolation region, and then an interlayer insulating film
133
made of silicon oxide is formed on the silicon nitride film
132
.
Then, a plurality of contact holes
134
a
,
134
d
are formed in the silicon nitride film
132
and the interlayer insulating film
133
by the photolithography technique. These contact holes
134
s
,
134
d
are formed on two silicide layers
131
s
,
131
d
in the active region. In this case, if miniaturization of the semiconductor device is considered, a diameter of the contact holes
134
s
,
134
d
cannot be formed to have a wide margin in size rather than the high-impurity concentration regions
129
s
,
129
d
and as a result the contact holes
134
s
,
134
d
can be formed to cross over the buried insulating film
123
.
Then, the wirings (not shown) are provided to the LDD structure impurity diffusion layers
129
s
,
129
d
via the contact holes
124
s
,
134
d.
With the above, the common SAC technique and the common BCL technique have been described.
Meanwhile, for example, as set forth in Patent Application Publication (KOKAI) 6-12765, it has been deduced that an etching rate of Si
3
N
4
can be enhanced rather than that of Si if one of CH
2
F
2
and CH
3
F is employed as an etching gas to etch a covering layer made of silic
Armstrong Westerman & Hattori, LLP
Chaudhuri Olik
Fujitsu Limited
Rao Shrinivas H.
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