Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2000-03-23
2002-01-01
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S057000, C257S522000, C438S149000, C438S411000
Reexamination Certificate
active
06335543
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-10099, filed on Mar. 24, 1999, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a polycrystalline silicon thin film transistor (Poly-Si TFT) and a method of manufacturing the same.
2. Description of Related Art
Conventional polycrystalline silicon thin film transistors (hereinafter referred to simply as “Poly-Si TFTs”) are commonly employed in high-density static random access memory cells (SRAMs) for load pull-up devices, as well as used for both switching elements and peripheral driver circuitry in large-area active-matrix liquid crystal displays (LCDs).
FIG. 1
is a plan view illustrating a typical Poly-Si TFT of a coplanar type for use in a liquid crystal display device, and
FIG. 2
is a cross-sectional view taken along line II—II of FIG.
1
. As shown in
FIGS. 1 and 2
, gate lines
60
are arranged in a transverse direction and data lines
70
are arranged in a longitudinal direction perpendicular to the gate lines
60
such that pixel regions having a pixel electrodes
40
is defined by the gate lines
60
and the data lines
70
. The Poly-Si TFT
50
is formed near the cross point of the gate lines
60
and the data lines
70
. The Poly-Si TFTs
50
have a gate electrode
60
a
extended from the gate line
60
, a source electrode
70
a
extended from the data line
70
, a drain electrode
70
b
contacted with the pixel electrode
40
, a polycrystalline silicon layer
90
a
as an active area of the Poly-Si TFT
50
. The overlapped portion
40
a
of the pixel electrode
40
and the gate line
60
function as capacitor electrodes.
A manufacturing method of the Poly-Si TFT described above will be explained in detail as follows. A buffer layer
30
made of SiNx, SiO
2
, or BCB (Benzocyclobutene) is formed on a transparent substrate
10
. Amorphous silicon is deposited on the buffer layer
30
and patterned to form an amorphous silicon layer (not shown). The amorphous silicon layer is heat-treated using a furnace annealing technique or a laser annealing technique to form a polycrystalline silicon layer
90
a.
A first insulating layer
55
of SiNx or SiO
2
is formed on the polycrystalline silicon layer
90
a
and the exposed buffer layer
30
. A metal layer of Cr, Al, or Mo is deposited over the polycrystalline silicon layer
90
a
and patterned to form the gate electrode
60
a.
Impurity ion gas is doped into the polycrystalline silicon layer
90
a
using the gate electrode
60
a
as a mask to form an ohmic contact layer on both ends of the polycrystalline silicon layer
90
a
to define source and drain regions
92
and
94
. At this point, the source and drain regions
92
and
94
become n
+
-type when the doped ion gas is one of a nitrogen group, while the source and drain regions
92
and
94
become p
+
-type when the doped ion gas is one of a boron group. Sequentially, a second insulating layer
8
is formed over the entire substrate
10
while covering the gate electrode
60
a
and the first insulating layer
55
. Then, contact holes
5
a
and
5
b
are formed to respectively expose the source and drain regions
92
and
94
. A metal layer of Cr, Al, or Mo is deposited on the second insulating layer
8
and patterned to form source and drain electrodes
70
a
and
70
b
respectively contacted with the source and drain regions
92
and
94
through the contact holes
5
a
and
5
b.
A third insulating layer
80
of SiNx, SiO
2
, or BCB is formed over the entire substrate while covering the source and drain electrodes
70
a
and
70
b.
A contact hole
80
a
is formed to expose the drain electrode
70
b.
Then, a pixel electrode
40
of ITO (Indium Tin Oxide) is formed on the third insulating layer
80
and contacts with the drain electrode
70
b
through the contact hole
80
a.
As shown in
FIG. 3
, the polycrystalline silicon layer
90
a
of the Poly-Si TFT has elevated grain boundaries
33
on an upper surface thereof, which are formed due to a heat transfer difference during the heat-treatment process for polycrystallization of the amorphous silicon layer. In other words, polycrystallization of a lower surface of the amorphous silicon layer is performed faster than the upper surface of the amorphous silicon layer. This is because heat of the lower surface of the amorphous silicon layer contacting with the buffer layer
30
transfers relatively faster than heat of the upper surface of the amorphous silicon layer contacting with nothing during the heat-treatment process, leading to a crystal growing speed difference between the upper and lower surfaces of the amorphous silicon layer. Such a crystal growing speed difference due to the heat transfer difference causes elevated grain boundaries on the upper surface of the polycrystalline silicon layer
90
a.
In more detail, heat transfers quickly from the amorphous silicon layer to the buffer layer
30
during the heat-treatment process leading to fast polycrystallization of the lower of the amorphous silicon layer, so the crystal tends to grow in a gravity direction. However, the buffer layer
30
prevents the crystals from growing in the gravity direction. Therefore, the crystals grow forward from the upper surface of the amorphous silicon layer that has a crystal growing speed relatively slower than the speed of the lower surface of the amorphous silicon layer.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a Poly-Si TFT having an improved field effect mobility.
In order to achieve the above object, the present invention provides a polycrystalline silicon thin film transistor connected to a gate line and a data line, including a source electrode contacting the data line; a gate electrode contacting the gate line; a drain electrode spaced apart from the source electrode; a polysilicon layer having upper and lower surfaces, the lower surface having a contacting area and a noncontacting area, the polysilicon layer being positioned between and contacting the source and the drain electrodes, and acting as a channel in which electrons flow; and a buffer layer positioned under the polysilicon layer, the buffer layer having a supporting portion, the supporting portion supporting the lower surface of the polysilicon layer through the contact area of the lower surface of the polysilicon layer, thereby forming a space between the buffer layer and the noncontacting area of the lower surface of the polysilicon layer.
The polysilicon layer has an “H” shape. The supporting portion has a corresponding shape to the polysilicon layer, or has two poles, each end of the poles contacting the lower surface of the silicon layer.
The present invention further provides a method of fabricating a thin film transistor, including the steps of providing a substrate; forming a buffer layer on the substrate; forming an amorphous silicon layer on the buffer layer; patterning the amorphous silicon layer; etching the buffer layer using the patterned amorphous silicon layer as a mask to form a noncontacting area in a bottom surface of the amorphous silicon layer; heat-treating the amorphous silicon layer to form a polysilicon layer; forming source and drain electrodes contacting the polysilicon layer; and forming a gate electrode between the source and the drain electrodes.
The heat-treating process is done using a laser annealing technique.
Other features, elements and advantages of the present invention will be described in detail below with reference to preferred embodiments of the present invention and the attached drawings.
REFERENCES:
patent: 5397904 (1995-03-01), Arney et al.
patent: 5614728 (1997-03-01), Akiyama
patent: 0783124 (1997-07-01), None
patent: 1100518 (1989-04-01), None
Lee Sanggul
Yi Jonghoon
Everhart Caridad
LG. Philips LCD Co. Ltd.
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