Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-07-22
2002-03-19
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S758010, C324S761010
Reexamination Certificate
active
06359452
ABSTRACT:
BACKGROUND OF THE INVENTION
1). Field of the Invention
The present invention generally relates to a method and apparatus for testing an electronic assembly. More specifically, the present invention relates to a method and apparatus for testing an electronic assembly comprising a printed circuit board and an electronics device such as an electronics package mounted to a first side of the electronics package, wherein a fixture is used with electrical pins contacting contact pads on a second side of the printed circuit board opposing the first side. The manner of contacting the printed circuit board, the printed circuit board itself, and aspects of the fixture are particularly suitable for high frequency testing.
2). Discussion of Related Art
Integrated circuits are usually manufactured in the form of a chip with a circuit formed in a surface of the chip. Such an integrated circuit is then mounted to a package substrate. The combination of the package substrate and the integrated circuit is called an electronics package. Electrical leads such as wireboarding wire or tape automated bonding (TAB) tape connect the integrated circuit to the package substrate. In other electronics packages the integrated circuit is mounted to a package substrate by an array of controlled collapse chip connect (C4) bumps which also place the integrated circuit in electrical communication with the package substrate.
The electronics package is then often mounted to a printed circuit board. In older assemblies the package substrate is glued or otherwise secured to the printed circuit board. Electrical wires extend from an opposing surface of the package substrate over an edge of the package substrate onto the printed circuit board, thereby placing the package substrate, and therefore also the integrated circuit, in electrical communication with the printed circuit board. Traces extend from the electrical wires to contact pads located around the package substrate on the printed circuit board. Pins of a test fixture can be brought into contact with the contact pads and an electrical tester connected to the electrical pins can be used to test the integrated circuit.
A large area is required around the package substrate on the printed circuit board in order to accommodate the contact pads, which increases the size and overall cost of the printed circuit board. Moreover, the traces on the printed circuit board increase resistance-capacitance delay, especially during high frequency testing, thus reducing signal integrity and limiting testing of the integrated circuit to lower frequencies.
Furthermore, a more recent development is to mount the package substrate to a printed circuit board by means of an array of solder balls located between the package substrate and the printed circuit board. The solder balls also connect the package substrate electrically to the printed circuit board. Traces may be formed on the printed circuit board, extending from the solder balls to contact pads around the electronics package. A primary advantage of mounting an electronics package to a printed circuit board by an array of solder balls is that a large number of balls can be used in the form of an array. However, a large number of solder balls only multiplies the problems associated with increased space on the printed circuit board and of resistance-capacitance delay.
What may therefore be required is a method and apparatus of testing an integrated circuit on an electronics package mounted to a printed circuit board, especially by means of an array of solder balls, wherein space is saved on the printed circuit board and, more particularly, wherein resistance-capacitance delay is reduced to facilitate high frequency testing.
SUMMARY OF THE INVENTION
According to one aspect of the invention a fixture for testing an electronic assembly including a printed circuit board is provided. The fixture includes a pin housing. An array of electrical pins are mounted to and extend from the pin housing. An electrical connector is within logic communication with the electrical pins. A structure is provided which aligns the pin housing with respect to the printed circuit board with the electrical pins facing the printed circuit board. A device is provided which serves to secure the pin housing to the printed circuit board.
The pin housing may include a test board, wherein the electrical connector is mounted to the test board. The electrical connector may be in logic communication with the electrical pins through traces formed on the test board.
A further aspect of the invention deals with the lengths of the electrical pins. The pins are preferably sufficiently short to allow for high frequency testing of the electronic assembly. The electrical pins are preferably less than 12 mm in length with an improvement in reliability for lengths less than 6 mm. The electrical pins are typically less than 3.5 mm, particularly for purposes of relaying test signals at frequencies above 300 MHz.
The structure for aligning the pin housing with respect to the printed circuit board may include an alignment shaft securable to the pin housing and extending through an alignment opening in the printed circuit board.
A clamping component may be securable to the pin housing with the printed circuit board located between the pin housing and the clamping component.
In order to depress a large number of electrical pins, typically in the range of between 300 and 1200 electrical pins, the device for securing the pin housing to the printed circuit board preferably includes a threaded portion.
According to another aspect of the invention, apparatus is provided for testing an electronic assembly including a printed circuit board. The apparatus includes a pin housing. An array of electrical pins, for contracting the printed circuit board, are mounted to and extend from the pin housing. An electrical tester is in logic communication with the electrical pins. The electrical tester may operate at at least 25 MHz and up to (but not limited to) 250 MHz.
In order for the electrical tester to accurately relay signals at high frequencies the electrical pins may be less than 6 mm in length, but preferably less than 3.5 mm in length.
According to a further aspect of the invention, a method of testing an electronic assembly comprising a printed circuit board and an electronic device mounted to a first side of the printed circuit board is provided. According to the method an array of contact pads on a second side of the printed circuit board opposing the first side is contacted with an array of electrical pins mounted to and extending from a pin housing. Signals are then relayed through the electrical pins between the electrical tester and the electronic device. Electrical signals are transmitted through the printed circuit board, which is a shorter, more reliable path with lower resistance-capacitance delay, being particularly viable for high frequency testing.
The electrical pins are preferably relatively short to further reduce resistance-capacitance delay. A relatively large number of electrical pins may be used, typically at least 300 pins and the printed circuit board is preferably secured to the pin housing by means of a threaded portion.
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patent: 5367253 (1994-11-01), Wood et al.
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patent: 5990697 (1999-11-01), Kazama
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patent: 6066957 (2000-05-01), Van Loan
Deb Anjan K.
Johnson W. Glen
Mothew Neil G. J.
Nortel Networks Limited
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