Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2001-11-28

2002-07-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185180, C365S185290

Reexamination Certificate

active

06418058

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-224232 filed on Aug. 6, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor memory device (EEPROM: Electrically Erasable Programmable ROM) including memory cell units in which a plurality of electrically rewritable memory cells are connected.
A NAND type EEPROM has been known as a kind of EEPROM enabling electrical rewriting. A single memory cell of NAND type EEPROM has a FETMOS (Floating gate Electrically erasable Tunneling MOS) structure stacking a floating gate (charge storage layer) and a control gate on a semiconductor substrate via an insulating film. A plurality of memory cells are connected in series while sharing common source and drain between every adjacent ones thereof to form a NAND type memory cell unit (hereinafter simply called NAND cell). Such NAND cells are arranged in form of a matrix to make up a memory cell array.
Drains at one-side ends of NAND cells aligned in the column direction of a memory cell array are commonly connected to a bit line via a selection gate transistor, and sources at the other common ends are connected to a common source line via a selection gate transistor, here again. Word lines of memory transistors and gate electrodes of selection transistors are commonly connected in the column direction of the memory cell array as a word line (control gate line) and a selection gate line, respectively.
This kind of NAND type EEPROM is known from the following literatures (1) and (2), for example.
(1) K. D. Suh, et al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE J. Solid-State Circuits, Vol. 30, pp. 1149-1156, November 1995
(2) Y. Iwata et al., “A 35 ns Cycle Time 3.3V Only 32 Mb RAND Flash EEPROM,” IEEE J. Solid-State Circuits, Vol. 30, pp. 1157-1164, November 1995.
FIG. 14
shows configuration of a single NAND cell block in a memory cell array of NAND cell type EEPROM. A plurality of memory cells M. are connected in series while sharing common source and drain between every adjacent ones thereof to form a NAND type memory cell unit. An end of each RAND cell is connected to a bit line BL via a selection transistor S
1
, and the other end thereof is connected to a common grounded line via a selection transistor S
2
. Control gates of memory cells M aligned in the horizontal direction in
FIG. 14
are commonly connected to a word line WL. Similarly, gates of the selection transistors S
1
and S
2
are commonly connected to selection gate lines SSL and GSL, respectively. The range of RAND cells driven by a single word line makes up a RAND cell block.
In general, a plurality of such RAND cell blocks are arranged in the bit line direction to form a memory cell array. Each RAND cell block is the minimum unit for data erasure, and so-called flash erasure (collective erasure) is conducted therefore. A series of memory cells aligned along a single selected word line within the RAND cell block is called one page, and one page is the unit for reading and writing data.
Each memory cell M stores data by representing the status with a positive threshold value due to injection of electrons into the floating gate (E (Enhancement) type status) and the status with a negative threshold value due to discharge of electrons from the floating gate (D (Depletion) type status) by using two values, respectively. For example, it is determined that the D type status is the status holding “1” data (erasure mode) and the E type status is the status holding “0” data (write mode). Additionally, it is defined that the operation shifting the threshold value of a memory cell holding “1” data toward the positive direction and changing it into the status holding “1” data is “write operation”, and operation shifting the threshold value of a memory cell holding “0” data toward the negative direction and changing it into the status holding “1” data is “erase operation”. In this specification, explanation is progressed according to such definition.
FIG. 15
shows relations among voltages of different portions data erase, read-out, write operations in a selected NAND cell block of a memory cell array. In erase operation, all word lines in a selected NAND cell block are set in 0V, and the selection gate lines SSL, GSL and bit line BL are held floating (F). Then a high positive erase voltage Vera (for example, erase pulse of 3 ms and 21V) to P-type wells of memory cells. As a result,in the selected block, an erase voltage is applied between wells and word lines, and electrons are released from the floating gate to the wells by a FN(Fowler-Nordheim) tunneling current. Consequently, memory cells in the NAND cell block become the erase mode of “1”.
At that time, in non-selected NAND cell blocks, there are no influences from the erase pulse because of capacity coupling of floating-status word lines and wells. The coupling ratio is calculated from the capacitance connected to word lines under the floating status. Actually, capacities of poly-silicon word lines and P wells in cell regions occupy an overwhelming part of the whole capacity, and the coupling ratio obtained from a result of actual measurement is as large as about 0.9 and disturbs the flow of FN tunneling current. For verifying erasure, it is judged whether threshold voltage has become −1V or lower in all memory cells in the selected block.
Data read-out operation is effected by applying 0V to the selected word line and a predetermined intermediate voltage Vread (a voltage independent from the threshold value and large enough to render the channel conductive) to non-selected word lines and selection gate lines, and by reading changes in potential of the bit lines BL caused by conduction or non-conduction of the selected memory cells.
Data write operation is effected by applying a positive high write voltage Vpgm to the selected word line, an intermediate voltage Vpass to non-selected word lines, Vcc to the selection gate line SSL on the part of bit lines, and Vss=0V to the selection gate line GSL on the part of common source line, and applying Vss to bit lines BL to write “0” in, and Vcc to bit lines prohibited to write (that is, bit lines to be maintained in the erase mode of “1”). At that time, in a selected memory cell connected to the bit line supplied with Vss, the channel potential is held in Vss, a large electric field between the control gate and the channel is applied, and electrons are injected from the channel to the floating gate due to a tunneling current. In the other non-selected memory cells connected to the same bit line and applied with Vpass, electric field is not sufficient for writing. Therefore, writing is not effected.
In memory cells along a bit line applied with Vcc, channels of the NAND cell are pre-charged to Vcc or Vcc-Vth (Vth is the threshold voltage of the selection transistor), and the selection transistor is cut off. Then, when the write voltage Vpgm and the intermediate voltage Vpass are applied to the control gates, the channel potential increases due to capacity coupling between the NAND cell channels in the floating status and the control gates applied with Vpgm or Vpass, and electron injection does not occur.
In this manner, only in the memory cell at the crossing point of the bit line applied with Vss and the selected word line applied with Vpgm, electrons are injected, and “0” is written. In memory cells prohibited to write in within the selected block, since the channel potential is determined by capacity coupling between word lines and channels, in order to apply a sufficiently high write prohibiting voltage, it is important to ensure sufficient initial charging of channels and increase the capacity coupling ratio between word lines and channels.
Coupling ratio B between word lines and channels is calculated by B=Cox/(Cox+Cj

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