Patent
1995-08-22
1998-09-01
Lall, Parshotam S.
G06F 938
Patent
active
058023402
ABSTRACT:
A method for speculatively performing store instructions in a parallel processing computer system, the computer system including a completion buffer unit, includes comparing statuses between a first store instruction and at least one second instruction in the completion buffer unit, the at least one second instruction scheduled for completion before the first store instruction, and speculatively completing the first store instruction before the at least one second instruction when the statuses of the first store instruction do not conflict with the at least one second instruction. In another method aspect, speculatively performing store instructions includes forming a general purpose register (GPR) allocation deallocation table, the table including status fields for a plurality of instructions in a completion buffer unit, comparing the status fields of each of the plurality of instructions to a store instruction of the plurality of instructions, and speculatively completing the store instruction when the status fields for the store instruction do not conflict with the status fields for the plurality of instructions.
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Mallick Soummya
Patel Rajesh B.
Coulter Kenneth R.
International Business Machines - Corporation
Lall Parshotam S.
Salys Casimer K.
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