Semiconductor device

Details Semiconductor device Semiconductor device

2008-07-22

2008-07-22

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S686000, C257SE25013

Reexamination Certificate

active

07402903

ABSTRACT:
Disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the insulation film without being in contact with the plural diffusion layer patterns and to pass through the insulation film and the semiconductor substrate. Further disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the diffusion layer pattern without being in contact with the insulation film and to pass through the diffusion layer pattern and the semiconductor substrate.

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patent: 2001/0045605 (2001-11-01), Miyashita et al.
patent: 2002/0079492 (2002-06-01), Koga
patent: 2002/0079525 (2002-06-01), Mayuzumi
patent: 2002/0084513 (2002-07-01), Siniaguine
patent: 2002/0115226 (2002-08-01), Mikawa et al.
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patent: 2003/0210534 (2003-11-01), Swan et al.
patent: 10-223833 (1998-08-01), None
patent: 11-195706 (1999-07-01), None
patent: 2003-203914 (2003-07-01), None
Nobuo Hayasaka, et al.; Multichip Semiconductor Device, Chip Therefor and Method of Formation Thereof; U.S. Appl. No. 09/377,486, filed Aug. 20, 1999.
Notice of Reason of Rejection, dated Jan. 28, 2005, issued by Japanese Patent Office, for Japanese Patent Application No. 2003-013919, and English-language translation thereof.

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