Truncated product partial canonical signed digit multiplier

Details Truncated product partial canonical signed digit multiplier Truncated product partial canonical signed digit multiplier

1988-04-21

1990-10-30

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

049673882

ABSTRACT:
A truncated product partial canonical signed digit (PCSD) multiplier is disclosed for use in a finite impulse response (FIR) digital filter. Each multiplier quantity is coded as two non-zero signed digits in an 8-bit word. Each non-zero signed digit is recoded into a four bit nibble for application to the multiplier. Each partial product output of the multiplier is truncated from 16 to 11 bits. The multiplier operations are performed in the sequence shift right, truncate, one's complement, add partial products and, according to the output of a logic control circuit, add one into an appropriate order.

REFERENCES:
patent: 3691359 (1972-09-01), Dell et al.
patent: 3919535 (1975-11-01), Vattuone
patent: 4122527 (1978-10-01), Swiatowiec
patent: 4597053 (1986-06-01), Chamberlin
Blaauw et al., "Binary Multiplication" IBM Tech. Disclosure Bulletin vol. 4, No. 11, Apr. 1962, pp. 32-34.

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