Multiport execution target delay queue FIFO array

Details Multiport execution target delay queue FIFO array Multiport execution target delay queue FIFO array

2011-08-09

2011-08-09

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S216000

Reexamination Certificate

active

07996655

ABSTRACT:
One embodiment provides a method of forwarding data in a processor. The method generally includes providing at least one cascaded delayed execution pipeline unit having at least a first pipeline and a second pipeline for executing first and second instructions in a common issue group, wherein the second pipeline executes the second instruction in a delayed manner relative to the execution of the first instruction in the first pipeline, storing results generated by an execution unit of the first pipeline in a first-in first-out (FIFO) storage target delay queue, determining if the target delay queue contains source data for executing the second instruction, and if the target delay queue contains source data for the second instruction, forwarding the source data for the second instruction from the target delay queue to an execution unit of the second pipeline.

REFERENCES:
patent: 6985150 (2006-01-01), Deering
patent: 7003649 (2006-02-01), Krishnan
patent: 2003/0154364 (2003-08-01), Peng et al.
patent: 2006/0149930 (2006-07-01), Murakami et al.
patent: 2007/0186080 (2007-08-01), Luick
Shen; Modern Processor Design: Fundamentals of Superscalar Processors; 2002; McGraw Hill.

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