Method and system for implementing efficient locking to...

Details Method and system for implementing efficient locking to... Method and system for implementing efficient locking to...

2011-08-30

2011-08-30

Doan, Nghia M (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

C716S053000, C716S054000, C716S055000, C716S101000, C716S104000, C716S110000, C716S118000, C716S119000, C716S139000, C716S107000, C712S009000, C712S010000, C712S011000, C712S015000, C718S102000, C718S103000, C718S104000, C718S105000, C718S106000

Reexamination Certificate

active

08010917

ABSTRACT:
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

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