Semiconductor device having field effect transistors

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357 231, 357 41, 357 44, H01L 2702, H01L 2978

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049672576

ABSTRACT:
A semiconductor device having field effect transistors (FETs) is provided. In the FET, a channel surface where a channel region and a gate electrode are opposed to each other is formed approximately vertical to a main surface of a substrate. A p type (n type) semiconductor region is formed on the main surface of the substrate, and a concave portion with a portion of side wall surfaces thereof being an exposed surface of the semiconductor region is formed. In the semiconductor region, n type (p type) drain and source regions are formed spaced apart from each other defining the channel region. A gate insulating layer is formed in the concave portion on the exposed surface of the semiconductor region on the channel region. A gate electrode is formed on the gate insulating layer in the concave portion. Consequently, the rate of the area occupied by one field effect transistor to the main surface of the substrate can be reduced. Therefore, a semiconductor device can be provided in which field effect transistors are integrated to a high degree without reducing channel length and without degrading performance of the transistors.

REFERENCES:
patent: 4835584 (1989-05-01), Lancaster
patent: 4835585 (1989-05-01), Panousis
patent: 4881105 (1989-11-01), Davari et al.
IBM Technical Disclosure Bulletin, vol. 29, No. 10, Trench Mosfets, Mar. 1987, pp. 4305-4307.
IEDM 85: "A Trench Transistor Cross-Point DRAM Cell", by W. F. Richardson et al, 29.6, 1985, pp. 714-717.

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