Parallel hardware arrangement for correlating an external...

Details Parallel hardware arrangement for correlating an external... Parallel hardware arrangement for correlating an external...

2008-04-15

2008-04-15

Chan, Wing (Department: 2619)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S475000

Reexamination Certificate

active

07359381

ABSTRACT:
An arrangement of data storage cells are accessed in parallel for correlating a transport address pair with a respective local association. In one embodiment, each cell may contain a transport address pair and a local association ID. In another embodiment, multiple stages of partitioned content addressable arrays may be employed, with at least a portion of the transport address pair used to access the first stage and at least a portion of an output from a preceding stage used to select a corresponding array in a succeeding stage.

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