Programmable processing elements interconnected by a communicati

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364229, 3642323, 3642402, 36424294, 3642598, 3642844, 3649314, 3649338, 364DIG1, G06F 900, G06F 1300, G06F 1516

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050939203

ABSTRACT:
An arrangement for implementing graph operations, generally, and circuit simulations in particular employing a plurality of substantially identical high speed special purpose processing elements (PE) that are flexibly interconnected through a switch to form a cluster. In addition to the processing element (PE) being programmable, the interconnection switch permits dynamically altered routing of signals between the processing elements. The processing elements include a queue unit which permits high speed asynchronous communication between the elements. Additional advantage is attained with a hierarchical arrangement where a plurality of clusters are interconnected in an n-cube arrangement, and all of the clusters communicate with a host computer.

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