Semiconductor chip with metallization levels, and a method...

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state

Reexamination Certificate

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C438S600000, C438S622000, C257SE21595

Reexamination Certificate

active

07393721

ABSTRACT:
A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in an uppermost metallization level (1). A further opening is produced in the metal surface (5), through which a focused ion beam is aimed at the interconnect structure (6) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.

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patent: 6458630 (2002-10-01), Daubenspeck et al.
patent: 2002/0182837 (2002-12-01), Daubenspeck et al.
patent: 2003/0205816 (2003-11-01), Janke
patent: WO 90/03046 (1990-03-01), None

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