Symmetrical clock distribution in multi-stage high speed...

Details Symmetrical clock distribution in multi-stage high speed... Symmetrical clock distribution in multi-stage high speed...

2008-01-15

2008-01-15

Ngo, Ricky Q. (Department: 2616)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S541000

Reexamination Certificate

active

07319706

ABSTRACT:
The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

REFERENCES:
patent: 4727541 (1988-02-01), Mori et al.
patent: 5726990 (1998-03-01), Shimada et al.
patent: 5940456 (1999-08-01), Chen et al.
patent: 6636532 (2003-10-01), Dorschky
patent: 2001/0005158 (2001-06-01), Okayasu
patent: 2003/0063626 (2003-04-01), Karlquist

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