Microprocessor with low power bus

Details Microprocessor with low power bus Microprocessor with low power bus

1993-01-22

1994-04-19

Chun, Debra A.

Boots, shoes, and leggings

364DIG1, 3642304, 3642401, 36424292, 364239, 3642731, 395750, G06F 13364, G06F 132

Patent

active

053054431

ABSTRACT:
A microprocessor provides a bus state referred to as "loop-back". This state holds the data bus at valid logic levels, without use of resistors, after a read transaction has been completed and there are no pending bus transactions. When this state is entered, the data just read from the data bus is driven back onto the data bus, and the device which had provided the data is placed in the tri-state (high-impedance) condition. This loop-back feature, combined with the fact that all other outputs are held at their previous values, provides for near-zero power dissipation on the bus. The inventive technique avoids the use of pull-up resistors, which are provided on prior art tri-state busses to ensure that the busses do not float and enter the threshold region where high power dissipation occurs.

REFERENCES:
patent: 4430585 (1984-02-01), Kirk, Jr.
patent: 4494192 (1985-01-01), Lew
patent: 4531068 (1985-07-01), Kraft
patent: 4941126 (1990-07-01), Haubursin
patent: 5087840 (1992-02-01), Davies
patent: 5109493 (1992-04-01), Banerjee
German, Elektronik, vol. 33, No. 7, Apr. 1984 Munchen De pp. 43-54; by Hans Eichel.

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