Electric lamp and discharge devices: systems – Current and/or voltage regulation
Reexamination Certificate
2008-01-29
2008-01-29
Vu, David H. (Department: 2821)
Electric lamp and discharge devices: systems
Current and/or voltage regulation
C315S219000, C315S224000, C315SDIG002
Reexamination Certificate
active
07323829
ABSTRACT:
A technique is described that reduces parasitic losses in circuits used to drive current through a load. An example of a system according to the technique includes four switches in series with five pins such that one pin is connected to ground. An example of an apparatus according to the technique may include four switches in series with two switches connected to ground and to a load and two switches connected to a power source. An example of a method according to the technique involves producing a voltage waveform having three phases.
REFERENCES:
patent: 5528192 (1996-06-01), Agiman et al.
patent: 5615093 (1997-03-01), Nalbant
patent: 5619402 (1997-04-01), Liu
patent: 5757173 (1998-05-01), Agiman
patent: 5892336 (1999-04-01), Lin et al.
patent: 5923129 (1999-07-01), Henry
patent: 5930121 (1999-07-01), Henry
patent: 6104146 (2000-08-01), Chou et al.
patent: 6198234 (2001-03-01), Henry
patent: 6198245 (2001-03-01), Du et al.
patent: 6259615 (2001-07-01), Lin
patent: 6307765 (2001-10-01), Choi
patent: 6396722 (2002-05-01), Lin
patent: 6459602 (2002-10-01), Lipcsei
patent: 6469922 (2002-10-01), Choi
patent: 6501234 (2002-12-01), Lin et al.
patent: 6507173 (2003-01-01), Spiridon et al.
patent: 6515881 (2003-02-01), Chou et al.
patent: 6531831 (2003-03-01), Chou et al.
patent: 6559606 (2003-05-01), Chou et al.
patent: 6570344 (2003-05-01), Lin
patent: 6654268 (2003-11-01), Choi
patent: 6657274 (2003-12-01), Comeau et al.
patent: 6756769 (2004-06-01), Bucur et al.
patent: 6781325 (2004-08-01), Lee et al.
patent: 6809938 (2004-10-01), Lin et al.
patent: 6853047 (2005-02-01), Comeau et al.
patent: 6856519 (2005-02-01), Lin et al.
patent: 6864669 (2005-03-01), Bucur
patent: 6870330 (2005-03-01), Choi
patent: 6873322 (2005-03-01), Hartular
patent: 6876157 (2005-04-01), Henry
patent: 6888338 (2005-05-01), Popescu-Stanesti et al.
patent: 6897698 (2005-05-01), Gheorghiu et al.
patent: 6900993 (2005-05-01), Lin et al.
patent: 6906497 (2005-06-01), Bucur et al.
patent: 6936975 (2005-08-01), Lin et al.
patent: 6946806 (2005-09-01), Choi
patent: 6956336 (2005-10-01), Ribarich
patent: 6979959 (2005-12-01), Henry
patent: 6999328 (2006-02-01), Lin
patent: 7023709 (2006-04-01), Lipcsei et al.
patent: 7057611 (2006-06-01), Lin et al.
patent: 7061183 (2006-06-01), Ball
patent: 7075245 (2006-07-01), Liu
patent: 7095392 (2006-08-01), Lin
patent: 7098605 (2006-08-01), Oh
patent: 7112929 (2006-09-01), Chiou
patent: 7112943 (2006-09-01), Bucur et al.
patent: 7120035 (2006-10-01), Lin et al.
patent: 7126289 (2006-10-01), Lin et al.
patent: 7141933 (2006-11-01), Ball
patent: 7157886 (2007-01-01), Agarwal et al.
patent: 7161309 (2007-01-01), Chiou et al.
patent: 7173382 (2007-02-01), Ball
patent: 7183724 (2007-02-01), Ball
patent: 7183727 (2007-02-01), Ferguson et al.
patent: 7187139 (2007-03-01), Jin
patent: 7187140 (2007-03-01), Ball
patent: 7190123 (2007-03-01), Lee et al.
patent: 7200017 (2007-04-01), Lin
patent: 2002/0180380 (2002-12-01), Lin
patent: 2005/0030776 (2005-02-01), Lin
patent: 2005/0093471 (2005-05-01), Jin
patent: 2005/0093482 (2005-05-01), Ball
patent: 2005/0093484 (2005-05-01), Ball
patent: 2005/0151716 (2005-07-01), Lin
patent: 2005/0174818 (2005-08-01), Lin et al.
patent: 2005/0225261 (2005-10-01), Jin
patent: 2006/0202635 (2006-09-01), Liu
patent: 2006/0232222 (2006-10-01), Liu et al.
patent: 2006/0279521 (2006-12-01), Lin
patent: 2007/0001627 (2007-01-01), Lin et al.
patent: 2007/0046217 (2007-03-01), Liu
patent: 2007/0047276 (2007-03-01), Lin et al.
patent: 2007/0085493 (2007-04-01), Kuo et al.
Chen Wei
Moyer James C.
Lu Zhou
Monolithic Power Systems, Inc.
Perkins Coie LLP
Vu David H.
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