Instruction encoding in a hardware simulation accelerator

Details Instruction encoding in a hardware simulation accelerator Instruction encoding in a hardware simulation accelerator

2011-01-04

2011-01-04

Silver, David (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

C703S015000, C716S030000, C716S030000

Reexamination Certificate

active

07865346

ABSTRACT:
A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.

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