Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1999-11-04
2000-12-19
Karlsen, Ernest
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324752, 324766, G01R 3126
Patent
active
061631639
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for characterizing a specimen of semiconductor material and, more particularly, to a method and apparatus determining parameters such as the doping concentration profile of a specimen of semiconductor material.
2. Description of Prior Art
Various methods for measurements of semiconductor surface and semiconductor/insulator interface parameters have been described. They can be classified into destructive and non-destructive. Examples of destructive methods are the secondary ion mass spectrometry and the four-point sensor method.
Non-destructive methods can be further classified into those requiring post-processing and those that don't (post-processing is defined as additional processing steps beyond those that define properties of semiconductor surface or semiconductor/insulator interface that are the goal of characterization). An example of a method that requires post-processing are traditional Metal-Insulator-Semiconductor Volt-Farad (MIS CV) measurements. They require presence of an insulator over the semiconductor surface and deposition of a metal layer over the insulator. Additional steps are costly, time-consuming and they can change the properties that were the goal of measurements.
Methods that do not require post-processing can be subdivided into contact and non-contact methods. Contact methods are defined as those that involve bringing the specimen into physical contact with materials or chemicals other than the ambient environment or materials and equipment that are used to handle specimens (semiconductor wafers) during normal processing steps, such as cleaning, annealing, implantation, etc. Since such methods require direct contact of a foreign material with the front side of the wafer there is a risk of contaminating the wafer, therefore they are not used with production wafers.
Finally, several non-contact methods for semiconductor surface/interface characterization are known in the field.
The apparatus described in U.S. Pat. No. 5,233,291 uses traditional CV methodology for measurement of the properties of semiconductor surface and semiconductor/insulator interface. The difference between the apparatus in U.S. Pat. No. 5,233,291 and MIS CV measurement systems is in the use of precisely controlled air gap as the insulating layer between the metal electrode and the semiconductor. Wafer proximity is determined by detecting the energy losses of the laser beam that undergoes total internal reflection on the surface of the transparent conductive electrode caused by interaction of the sample with the evanescent beam. The electrode is suspended at submicron distance from the sample, this distance as well as tip and tilt being monitored by three capacitive sensors and controlled by three piezo actuators in real time during the measurements.
In order to calculate semiconductor parameters using CV methods, it is necessary to know the width of the depletion layer in the semiconductor. W.sub.d. In the method in U.S. Pat. No. 5,233,281, W.sub.d is calculated from the capacitance of the depletion layer, which in turn is calculated from the total capacitance between the metal electrode and the semiconductor substrate. times during the measurement, which means either measuring the air gap, holding it fixed with substantial precision during the measurements of electrical parameters of the sample, or being able to calculate it at all times during the measurement based on previously characterizing the behavior of the air gap.
Additionally, the method described in U.S. Pat. No. 5,233,291 is not well suited for measurements of samples with poorly passivated semiconductor/insulator interface, e.g. non-passivated wafers of epitaxially grown films, because of the presence of slow surface states which may recharge during the measurements and thus affect both the measurements of C.sub.Si.sup.-1.
The surface photovoltage method described in U.S. Pat. No. 4,827,212 to E. Kamienicki, which patent is incorporated
REFERENCES:
patent: 3857095 (1974-12-01), Mitchie et al.
patent: 4812756 (1989-03-01), Curtis et al.
patent: 5091691 (1992-02-01), Kamieniecki et al.
patent: 5442297 (1995-08-01), Verkuil
Domenicali Peter L.
Field Alan H.
Kohn Charles M.
Liberman Sergey
Marston Glendon P.
Karlsen Ernest
Semitest Inc.
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