Structure and method for stacked wafer fabrication

Details Structure and method for stacked wafer fabrication Structure and method for stacked wafer fabrication

2011-06-07

2011-06-07

Stark, Jarrett J (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S459000, C438S462000, C257SE21503, C257SE21511

Reexamination Certificate

active

07955895

ABSTRACT:
A method for fabricating stacked wafers is provided. In one embodiment, the method comprises providing a wafer having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies is provided, each of the die bonded to one of the plurality of semiconductor chips. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material. The non-chip side of the wafer is thinned to an intended thickness. The wafer is then diced to separate the wafer into individual semiconductor packages.

REFERENCES:
patent: 6599778 (2003-07-01), Pogge et al.
patent: 7709295 (2010-05-01), Fujimura
patent: 2007/0184660 (2007-08-01), Fujimura
patent: 1592965 (2005-03-01), None
patent: 101022081 (2007-08-01), None

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