Multilayer wiring structure and semiconductor device having the

Details Multilayer wiring structure and semiconductor device having the Multilayer wiring structure and semiconductor device having the

1999-05-21

2000-12-19

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257786, 257774, 257781, 438623, H01L 2348, H01L 2352, H01L 2940

Patent

active

061630756

ABSTRACT:
In a multilayer wiring structure, a plurality of wiring layers (9, 11, 13) are formed on an inorganic lowermost insulating film (2) formed on a silicon substrate (1), and organic interlayer insulating films (14, 15, 16, 17, 18) are interposed between the respective adjacent wiring layers. Via metal (8, 10, 12) are formed in the inorganic lowermost insulating film (2) and the organic interlayer insulating films (15, 17), and openings having the shape corresponding to an electrode pad are formed in the organic interlayer insulating films (14, 15, 16, 17, 18), and these openings are filled with metal material to form metal film patterns (3, 4, 6, 5, 7), whereby the electrode pad is constructed as the laminate body of the metal film patterns (3, 4, 6, 5, 7). Accordingly, even when organic material having a low dielectric constant is used for the interlayer insulating films, durability of an electrode portion to impacts in a bonding process is enhanced, and both of reduction in parasitic capacitance and enhancement in strength of the electrode portion can be achieved.

REFERENCES:
patent: 5036383 (1991-07-01), Mori
patent: 5060051 (1991-10-01), Osuda
patent: 5442239 (1995-08-01), DiGiacomo et al.
patent: 5567981 (1996-10-01), Bhansali et al.
patent: 5739587 (1998-04-01), Sato
patent: 5886410 (1999-03-01), Chiang et al.
patent: 5923088 (1999-07-01), Shiue et al.

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