Justification decision circuit for an arrangement for bit rate a

Details Justification decision circuit for an arrangement for bit rate a Justification decision circuit for an arrangement for bit rate a

1991-08-29

1993-11-16

Kuntz, Curtis

Pulse or digital communications

Spread spectrum

Direct sequence

370102, 375118, H04L 700, H04L 2536

Patent

active

052630560

ABSTRACT:
A single signal is formed from two plesiochronous signals. The first signal's data are written in parallel in groups of n bits each. Writing and reading are controlled by respective counters, whose counts are also provided to a subtractor. A control loop for bit rate justification is formed by the subtractor, a controller and the read counter. A track counter counts the stuffed bits modulo n, and stops the read counter for one clock period after each n stuffed bits. The mean value of the subtractor output and the count of the track counter are set off against each other, and their result is used for justification formation and a preparation signal for incrementing the track counter.

REFERENCES:
patent: 4941156 (1990-07-01), Stern et al.
patent: 5119406 (1992-06-01), Kramer
patent: 5132970 (1992-07-01), Urbansky

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