Clock synchronization circuit

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S354000, C375S357000, C375S359000, C375S363000, C327S141000, C455S132000, C455S504000

Reexamination Certificate

active

07920664

ABSTRACT:
A clock synchronization circuit includes a clock generation circuit generating a sampling clock for sampling a received signal from an output of a local oscillator, a phase error detection circuit finding a phase error between sampling timing of the sampling clock and ideal sampling timing, and a timing correction circuit finding a correction quantity to correct a frequency error between a frequency of the sampling clock and a frequency of the ideal sampling timing and the phase error every sampling timing of the sampling clock, and outputting a sampling value interpolated according to the found correction quantity.

REFERENCES:
patent: 5018166 (1991-05-01), Tjahjadi et al.
patent: 5696639 (1997-12-01), Spurbeck et al.
patent: 5812336 (1998-09-01), Spurbeck et al.
patent: 5844920 (1998-12-01), Zook et al.
patent: 5909332 (1999-06-01), Spurbeck et al.
patent: 6111710 (2000-08-01), Feyh et al.
patent: 6411658 (2002-06-01), Sasaki
patent: 7093151 (2006-08-01), Williams
patent: 7456682 (2008-11-01), Adachi
patent: 2004/0164798 (2004-08-01), Adachi et al.
patent: 2006/0189295 (2006-08-01), Adachi
patent: 2006/0203937 (2006-09-01), Burgio
patent: 2009/0189648 (2009-07-01), Hochleitner et al.
patent: 0609095 (1994-08-01), None
patent: 0881764 (1998-12-01), None
patent: 06284159 (1994-10-01), None
patent: 08167841 (1996-06-01), None
patent: 2000049882 (2000-02-01), None
patent: 2000349745 (2000-12-01), None
patent: 2001237908 (2001-08-01), None
patent: 2003330569 (2003-11-01), None
patent: 2004064469 (2004-02-01), None
patent: 9812836 (1998-03-01), None
European Search Report for EP 07 01 8395 completed Sep. 1, 2009.
J. Bao et al., “A New Timing Recovery Method for DTV Receivers”, IEEE Transactions on Consumer Electronics, vol. 44, No. 4, Nov. 1998, pp. 1243-1248, XP000871421.
F. M. Gardner, “Interpolation in Digital Modems—Part I : Fundamentals”. IEEE Transactions on Communications, vol. 41, No. 3, Mar. 1993, pp. 501-507, XP000372693.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Clock synchronization circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock synchronization circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock synchronization circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2724226

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.