Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-03-08
2011-03-08
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S110000, C716S116000
Reexamination Certificate
active
07904860
ABSTRACT:
A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.
REFERENCES:
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5298866 (1994-03-01), Kaplinsky
patent: 5369640 (1994-11-01), Watson et al.
patent: 5384497 (1995-01-01), Britton et al.
patent: 5391942 (1995-02-01), El-Ayat et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5475830 (1995-12-01), Chen et al.
patent: 5526278 (1996-06-01), Powell
patent: 5648913 (1997-07-01), Bennett et al.
patent: 5717229 (1998-02-01), Zhu
patent: 5790479 (1998-08-01), Conn
patent: 5943490 (1999-08-01), Sample
patent: 6006025 (1999-12-01), Cook et al.
patent: 6177844 (2001-01-01), Sung et al.
patent: 6204690 (2001-03-01), Young et al.
patent: 6292020 (2001-09-01), Crabill
patent: 6327696 (2001-12-01), Mahajan
patent: 6373288 (2002-04-01), Ganzelmi et al.
patent: 6396303 (2002-05-01), Young
patent: 6446249 (2002-09-01), Wang et al.
patent: 6609241 (2003-08-01), Yonemori
patent: 6651232 (2003-11-01), Pileggi et al.
patent: 6661254 (2003-12-01), Agrawal et al.
patent: 6862548 (2005-03-01), Chan
patent: 6952813 (2005-10-01), Rahut
U.S. Appl. No. 11/200,686, filed Aug. 10, 2005, Rahut.
Rubinstein, Jorge et al., “Signal Delay in RC Tree Networks,”IEEE Transactions on Computer-Aided Design, Jul. 1983, pp. 202-211, vol. CAD-2, No. 3.
Elmore, W. C. , “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,”J. Appl. Phys., Jan. 1948, pp. 55-63, vol. 19, Issue 1.
King John J.
Levin Naum B
Webostad W. Eric
Xilinx , Inc.
LandOfFree
Method and apparatus for selecting programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for selecting programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for selecting programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2724063