Simultaneous switching noise analysis using superposition...

Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression

Reexamination Certificate

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C703S013000, C703S014000, C703S018000, C324S613000, C324S628000

Reexamination Certificate

active

07983880

ABSTRACT:
Extended linear superposition methods, computer program products and systems to calculate Simultaneous Switching Noise (SSN) on victim Input/Output (I/O) pins of an electronic component caused by aggressor I/O pins is provided. A method includes calculating the quiet output voltage on a victim pin caused by the power supply only, and then calculating an aggressor noise response induced on the victim pin caused by a single aggressor pin and the power supply. To calculate SSN for a combination of aggressors, the SSNs for the different aggressors are linearly combined, and then the effects of the power supply are discounted by using the calculated quiet output voltage. Additionally, a linear victim substitution model is introduced to replace a full buffer model for a victim pin with a resistor with different resistance values depending on the induced voltage. Further, an alternate transmission line model is introduced to simplify SSN simulations of transmission lines.

REFERENCES:
patent: 5280237 (1994-01-01), Buks
patent: 5477460 (1995-12-01), Vakirtzis et al.
patent: 6029117 (2000-02-01), Devgan
patent: 6353917 (2002-03-01), Muddu et al.
patent: 6405348 (2002-06-01), Fallah-Tehrani et al.
patent: 6523149 (2003-02-01), Mehrotra et al.
patent: 6545497 (2003-04-01), Hebert et al.
patent: 6564355 (2003-05-01), Smith et al.
patent: 6587815 (2003-07-01), Aingaran et al.
patent: 6772403 (2004-08-01), Sasaki
patent: 6785628 (2004-08-01), Corr
patent: 6788098 (2004-09-01), Alani et al.
patent: 6799153 (2004-09-01), Sirichotiyakul et al.
patent: 6951001 (2005-09-01), Chen
patent: 7159160 (2007-01-01), Yoh et al.
patent: 7181716 (2007-02-01), Dahroug
patent: 7279907 (2007-10-01), Phoon et al.
patent: 7346867 (2008-03-01), Su et al.
patent: 7562323 (2009-07-01), Bai et al.
patent: 7595679 (2009-09-01), Popovich et al.
patent: 7630845 (2009-12-01), Shibata et al.
patent: 7685549 (2010-03-01), Sinha et al.
patent: 7788620 (2010-08-01), Xue et al.
patent: 2004/0034840 (2004-02-01), Chen
patent: 2005/0099186 (2005-05-01), Parker et al.
patent: 2005/0268264 (2005-12-01), Nagai
patent: 2005/0283668 (2005-12-01), Ishikawa
patent: 2007/0200586 (2007-08-01), Phoon et al.
patent: 2008/0027662 (2008-01-01), Kouzaki et al.
patent: 2009/0192777 (2009-07-01), Clement et al.
patent: 2009/0288050 (2009-11-01), Celik et al.
S. Chun, M. Swaminathan, L. Smith, J. Srinivasan, Z. Jin, and M. Iyer, “Modeling of Simultaneous Switching Noise in High Speed System” vol. 24, No. 2, May 2001 IEEE, pp. 132-142.

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