Software verification

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07930659

ABSTRACT:
A system and method is disclosed for formal verification of software programs that advantageously improves performance of an abstraction-refinement loop in the verification system.

REFERENCES:
patent: 5652835 (1997-07-01), Miller
patent: 5963739 (1999-10-01), Homeier
patent: 6643827 (2003-11-01), Yang
patent: 7283945 (2007-10-01), Rajan
patent: 7587707 (2009-09-01), Ball et al.
patent: 2003/0204834 (2003-10-01), Ball et al.
patent: 2005/0166167 (2005-07-01), Ivancic et al.
patent: 2005/0229044 (2005-10-01), Ball
patent: 2005/0235257 (2005-10-01), Ball et al.
patent: 2007/0005633 (2007-01-01), Ball et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Software verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Software verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Software verification will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2718493

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.