Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2011-06-14
2011-06-14
Sandvik, Benjamin P (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S793000, C257SE23119
Reexamination Certificate
active
07960825
ABSTRACT:
A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.
REFERENCES:
patent: 5136360 (1992-08-01), Harada et al.
patent: 5384488 (1995-01-01), Golshan et al.
patent: 5854740 (1998-12-01), Cha
patent: 5969424 (1999-10-01), Matsuki et al.
patent: 6066877 (2000-05-01), Williams et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6300234 (2001-10-01), Flynn et al.
patent: 6376353 (2002-04-01), Zhou et al.
patent: 6383916 (2002-05-01), Lin
patent: 6410435 (2002-06-01), Ryan
patent: 6476506 (2002-11-01), O'Connor et al.
patent: 6476507 (2002-11-01), Takehara
patent: 6593222 (2003-07-01), Smoak
patent: 6593649 (2003-07-01), Lin et al.
patent: 6605528 (2003-08-01), Lin et al.
patent: 6649509 (2003-11-01), Lin et al.
patent: 6683380 (2004-01-01), Efland et al.
patent: 6756295 (2004-06-01), Lin et al.
patent: 6762115 (2004-07-01), Lin et al.
patent: 6798050 (2004-09-01), Homma et al.
patent: 6800555 (2004-10-01), Test et al.
patent: 6844631 (2005-01-01), Yong et al.
patent: 6979647 (2005-12-01), Bojkov et al.
patent: 7060607 (2006-06-01), Efland
patent: 7230340 (2007-06-01), Lin
patent: 7271489 (2007-09-01), Lin et al.
patent: 7319277 (2008-01-01), Lin
patent: 7355282 (2008-04-01), Lin et al.
patent: 7372161 (2008-05-01), Lin et al.
patent: 7381642 (2008-06-01), Lin et al.
patent: 7393772 (2008-07-01), Gleixner et al.
patent: 7394161 (2008-07-01), Kuo et al.
patent: 7416971 (2008-08-01), Lin et al.
patent: 7420276 (2008-09-01), Lin et al.
patent: 7423346 (2008-09-01), Lin et al.
patent: 7468545 (2008-12-01), Lin et al.
patent: 7470927 (2008-12-01), Lee et al.
patent: 7470997 (2008-12-01), Lin et al.
patent: 7473999 (2009-01-01), Lin et al.
patent: 7508059 (2009-03-01), Lin et al.
patent: 7582556 (2009-09-01), Lin et al.
patent: 2001/0035452 (2001-11-01), Test et al.
patent: 2001/0051426 (2001-12-01), Pozder et al.
patent: 2002/0000671 (2002-01-01), Zuniga et al.
patent: 2002/0043723 (2002-04-01), Shimizu et al.
patent: 2003/0222295 (2003-12-01), Lin
patent: 2004/0070042 (2004-04-01), Lee et al.
patent: 2005/0189633 (2005-09-01), Wang et al.
patent: 2006/0079019 (2006-04-01), Kim
patent: 2006/0186180 (2006-08-01), Bosco
patent: 2007/0045757 (2007-03-01), Matsubara et al.
patent: 2007/0045855 (2007-03-01), Lo et al.
patent: 2007/0205520 (2007-09-01), Chou et al.
patent: 2007/0212869 (2007-09-01), Chou et al.
patent: 2007/0275503 (2007-11-01), Lin et al.
patent: 2008/0001290 (2008-01-01), Chou et al.
patent: 2008/0042280 (2008-02-01), Lin et al.
patent: 2008/0080111 (2008-04-01), Lin et al.
Mistry, K. et al. “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (2003), pp. 1105-1110.
Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing,” Electronic Components and Technology Conference (2006) pgs. 1611-1615.
Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI Circuits,” Materials Research Society Symposium Proceedings VLSI V (1990) pp. 369-373.
Roesch, W. et al. “Cycling copper flip chip interconnects,” Microelectronics Reliability, 44 (2004) pp. 1047-1054.
Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and Reliability,” International Electron Devices Meeting (2006) pp. 1-4.
Yeoh, T-S. “ESD Effects on Power Supply Clamps,” Proceedings of the 6th International Sympoisum on Physical & Failure Analysis of Integrated Circuits (1997) pp. 121-124.
Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 773-776.
Venkatesan, S. et al. “A High Performance 1.8V, 0.20 pm CMOS Technology with Copper Metallization,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 769-772.
Jenei, S. et al. “High Q Inductor Add-on Module in Thick Cu/SiLK™ single damascene,” Proceedings from the IEEE International Interconnect Technology Conference (2001) pp. 107-109.
Groves, R. et al. “High Q Inductors in a SiGe BiCMOS Process Utilizing a Thick Metal Process Add-on Module,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (1999) pp. 149-152.
Sakran, N. et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor,” IEEE International Solid-State Circuits Conference, Session 5, Microprocessors, 5.6 (2007) pp. 106-107, p. 590.
Kumar, R. et al. “A Family of 45nm IA Processors,” IEEE International Solid-State Circuits Conference, Session 3, Microprocessor Technologies, 3.2 (2009) pp. 58-59.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) Presentation Slides 1-66.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) pp. 23-28.
Ingerly, D. et al. “Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing,” International Interconnect Technology Conference (2008) pp. 216-218.
Kurd, N. et al. “Next Generation Intel® Micro-architecture (Nehalem) Clocking Architecture,” Symposium on VLSI Circuits Digest of Technical Papers (2008) pp. 62-63.
Maloney, T. et al. “Novel Clamp Circuits for IC Power Supply Protection,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part C, vol. 19, No. 3 (Jul. 1996) pp. 150-161.
Geffken, R. M. “An Overview of Polyimide Use in Integrated Circuits and Packaging,” Proceedings of the Third International Symposium on Ultra Large Scale Integration Science and Technology (1991) pp. 667-677.
Luther, B. et al. “Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices,” Proceedings of the 10th International IEEE VLSI Multilevel Interconnection Conference (1993) pp. 15-21.
Master, R. et al. “Ceramic Mini-Ball Grid Array Package for High Speed Device,” Proceedings from the 45th Electronic Components and Technology Conference (1995) pp. 46-50.
Maloney, T. et al. “Stacked PMOS Clamps for High Voltage Power Supply Protection,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings (1999) pp. 70-77.
Lin, M.S. et al. “A New System-on-a-Chip (SOC) Technology—High Q Post Passivation Inductors,” Proceedings from the 53rd Electronic Components and Technology Conference (May 30, 2003) pp. 1503-1509.
MEGIC Corp. “MEGIC way to system solutions through bumping and redistribution,” (Brochure) (Feb. 6, 2004) pp. 1-3.
Lin, M.S. “Post Passivation Technology™—Megic ® Way to System Solutions,”Presentation given at TSMC Technology Symposium, Japa
McDermott Will & Emery LLP
Megica Corporation
Sandvik Benjamin P
Soderholm Krista
LandOfFree
Chip package and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chip package and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip package and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2716044