Slave network interface circuit for improving parallelism of...

Details Slave network interface circuit for improving parallelism of... Slave network interface circuit for improving parallelism of...

2011-03-29

2011-03-29

Mills, Donald L (Department: 2462)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C709S209000, C709S250000

Reexamination Certificate

active

07916720

ABSTRACT:
There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

REFERENCES:
patent: 2003/0229741 (2003-12-01), Stuber et al.
patent: 2005/0204084 (2005-09-01), Joe et al.
patent: 1020040032376 (2004-04-01), None
patent: 102060067802 (2006-06-01), None
patent: 1020060071075 (2006-06-01), None
Se-Joong Lee, et al: “An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip;” (2003 IEEE International Solid-State Circuits Conference, Session 26, Embedded and Digital Systems, Paper 26.6, pp. 1-2 2003).
Kangmin Lee, et al; “A Distributed Crossbar Switch Scheduler for On-Chip Networks;” (CICC, 2004).

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