Nonvolatile semiconductor memory system

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185110, C365S185220, C365S185080

Reexamination Certificate

active

08009480

ABSTRACT:
According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.

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patent: 2005/0068802 (2005-03-01), Tanaka
patent: 2006/0227624 (2006-10-01), Shiga
patent: 2006/0274566 (2006-12-01), Takashima et al.
patent: 2007/0253256 (2007-11-01), Aritome
patent: 2006186359 (2006-07-01), None

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