Method for non-selective shallow trench isolation reactive...

Details Method for non-selective shallow trench isolation reactive... Method for non-selective shallow trench isolation reactive...

2011-01-18

2011-01-18

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S309000, C438S353000, C438S359000, C438S405000

Reexamination Certificate

active

07871893

ABSTRACT:
Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

REFERENCES:
patent: 6555891 (2003-04-01), Furukawa et al.
patent: 7071072 (2006-07-01), Mo et al.
patent: 7118986 (2006-10-01), Steigerwalt et al.
patent: 2006/0105536 (2006-05-01), Cheng et al.
patent: 2008/0085593 (2008-04-01), Miyagawa

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