Systems and methods for a PLL-adjusted reference clock

Details Systems and methods for a PLL-adjusted reference clock Systems and methods for a PLL-adjusted reference clock

2011-04-19

2011-04-19

Pascal, Robert (Department: 2817)

Telecommunications

Transmitter and receiver at same station

With frequency stabilization

C455S260000, C331S172000, C375S371000, C375S376000

Reexamination Certificate

active

07929919

ABSTRACT:
A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.

REFERENCES:
patent: 6714765 (2004-03-01), Kimppa
patent: 7656323 (2010-02-01), Bereza et al.
patent: 2004/0053595 (2004-03-01), Shinbo et al.
patent: 2009/0156149 (2009-06-01), Plevridis et al.

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