Semiconductor integrated circuit having post-package testing fun

Details Semiconductor integrated circuit having post-package testing fun Semiconductor integrated circuit having post-package testing fun

1992-04-15

1993-11-16

Nguyen, Hoa T.

Excavating

371 402, G06F 1100, H03M 1300

Patent

active

052630315

ABSTRACT:
In a semiconductor integrated circuit including therein an electrically writable non-volatile semiconductor memory (10) and an error detection and correction circuit (3) for detecting and correcting an error of data read out from the semiconductor memory, there is provided an output selection register (6) set with a register setting signal (RS) so as to output a selection signal (R) having the level of the stored content of the output selection register itself. A selection signal switching circuit (7) receives the selection signal (R) from the output selection register (6) and another selection signal (S) from an output selection memory cell section (4) of the non-volatile semiconductor memory (10). The selection signal switching circuit (7) selects one of the received selection signals in accordance with a test signal (TS) and outputs the selected selection signal (DS) to a data selection circuit (5). With this arrangement, even after the semiconductor integrated circuit is assembled in a package or a system both of which do not allow to erase the content of the memory, it is possible to verify the operation of the error detection and correction circuit (3).

REFERENCES:
patent: 4858236 (1989-08-01), Ogasawara
patent: 4965828 (1990-10-01), Ergott, Jr. et al.

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