Device for implementing a sum of products expression

Details Device for implementing a sum of products expression Device for implementing a sum of products expression

2011-03-29

2011-03-29

Bullock, Jr., Lewis A (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07917569

ABSTRACT:
A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.

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IEEE Transactions on Circuits and Systems-11: Analog and Digital Signal Processing, vol. 43, No. IO, Oct. 1996, “Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers” Richard I. Hartley, Member, IEEE.

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