Delay locked loop circuit and semiconductor memory device...

Details Delay locked loop circuit and semiconductor memory device... Delay locked loop circuit and semiconductor memory device...

2011-05-24

2011-05-24

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07948289

ABSTRACT:
The present invention relates to a delay locked loop (DLL) circuit. The DLL circuit includes a phase comparator configured to compare a phase of a source clock with a phase of a feedback clock and generate a delay locking signal based on the comparison result, a clock delay configured to delay the source clock in response to the delay locking signal for locking delay, output the delayed source clock as a delay locked clock, and generate a delay end signal when a delay amount has reached a delay limit, a delay replica model configured to reflect a delay time of an output path of the source clock at the delay locked clock and output the reflected clock as the feedback clock, and a delay locking operation controller configured to terminate a delay locking operation in response to the delay locking signal and the delay end signal.

REFERENCES:
patent: 5552727 (1996-09-01), Nakao
patent: 5995424 (1999-11-01), Lawrence et al.
patent: 7099232 (2006-08-01), Kwak
patent: 7724050 (2010-05-01), Lee
patent: 2005/0249027 (2005-11-01), Kwak
patent: 2010/0201414 (2010-08-01), Oh
patent: 100295210 (2001-07-01), None
patent: 1020070038669 (2007-04-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Dec. 22, 2010.

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