Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2011-03-08
2011-03-08
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185180
Reexamination Certificate
active
07903469
ABSTRACT:
A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected to both ends of the plurality of memory cells respectively, a plurality of word lines and a plurality of bit lines which are connected to the plurality of memory cells and a data read control part wherein at least one of the memory cells is selected and when data is read from that memory cell a read pass voltage is applied to a word line which is connected to a non-selected memory cell other than the selected memory cell, and after applying the read pass voltage a voltage is applied to a control gate of the first selection transistor or the second selection transistor, and when applying the read pass voltage, the read pass voltage which is applied to the word line which is connected to at least one of the non-selected memory cells which is adjacent to the first selection transistor or the second selection transistor, is made lower than the read pass voltage which is applied to the word line which is connected to another cell of the non-selected memory cells.
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U.S. Appl. No. 12/621,913, filed Nov. 19, 2009, Watanabe.
Iwai Makoto
Watanabe Yoshihisa
Ho Hoai V
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Radke Jay
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