Delay adjusting method, and delay circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S147000, C327S277000

Reexamination Certificate

active

07977988

ABSTRACT:
A variable delay circuit1includes: a multistage delay circuit20constructed by connecting delay elements D1to Dn in series; a selecting unit21which selects one delayed signal obtained by introducing different amounts of delay by passing a reference clock through one or more of the delay elements D1to Dn; a decision unit23which, at decision timing synchronized to the reference clock, makes a decision on the logic state of each delayed signal sequentially selected from among the plurality of delayed signals; and a changing point detection unit24which detects at least two delay elements Dm and Dk where a change has occurred in the logic state of the reference clock at the decision timing, and wherein the difference (k−m) between the numbers of delay elements through which the clock signal has passed until reaching one of the two detected delay elements Dm and Dk is used as the number of delay elements that provides a desired delay time.

REFERENCES:
patent: 5451894 (1995-09-01), Guo
patent: 5995441 (1999-11-01), Kato et al.
patent: 6178123 (2001-01-01), Kato et al.
patent: 6281725 (2001-08-01), Hanzawa et al.
patent: 6570419 (2003-05-01), Hanzawa et al.
patent: 6756833 (2004-06-01), Miura
patent: 09-0321590 (1997-12-01), None
patent: 11-306757 (1999-11-01), None
patent: 2000-59209 (2000-02-01), None
patent: 2003-023343 (2003-01-01), None
International Search Report of PCT/JP2007/057220, Mailing Date of May 15, 2007.

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