Parametric timing analysis

Details Parametric timing analysis Parametric timing analysis

2011-06-28

2011-06-28

Silver, David (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Modeling by mathematical expression

Reexamination Certificate

active

07970590

ABSTRACT:
Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their timing performance. Timing analysis is susceptible to variation in circuit components due to fabrication process variation. Process variation is introduced as worst-case conditions or statistical probabilities. More accurate process variation is modeled by for timing sensitivity with Parametric Elmore Delay. Parametric Elmore Delay introduces effects on circuit components as parameters in the conventional Elmore Delay definition to model fabrication process variation in the timing analysis. Delay variance demonstrates sensitivities to process and design factors. Parametric timing analysis is used to anticipate fabrication yield and identify potential improvements in the design or fabrication process.

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