Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-01-04
2011-01-04
Clark, S. V (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S108000
Reexamination Certificate
active
07863095
ABSTRACT:
A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces.
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Harada Tatsuya
Ito Hiroyuki
Okuzawa Nobuyuki
Sasaki Yoshitaka
Sueki Satoru
Clark S. V
Headway Technologies Inc.
Oliff & Berridg,e PLC
TDK Corporation
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