Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – With current flow along specified crystal axis
Reexamination Certificate
2011-05-10
2011-05-10
Gurley, Lynne A (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
With current flow along specified crystal axis
C257S213000, C257SE21410, C257SE29262, C438S150000
Reexamination Certificate
active
07939862
ABSTRACT:
Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.
REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 7339213 (2008-03-01), Maeda et al.
patent: 2005/0191795 (2005-09-01), Chidambarrao et al.
patent: 2005/0280103 (2005-12-01), Langdo et al.
patent: 2006/0284255 (2006-12-01), Shin et al.
Standard. (2007). In the American Heritage® Dictionary of the English Language. Boston, MA: Houghton Mifflin. Retrieved Jul. 2, 2009, from http://www.credoreference.com/entry/hmdictenglang/standard.
Huang et al.: “Sub-50 nm P-Channel FinFet”, IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Moroz et al.: “Analyzing Strained-Silicon Option for Stress-Engineering Transistors”, Solid State Technology, Jul. 2004 Edition, Copyright 2004 by PennWell Corporation, 3 pages.
Moroz et al.: “Options At the 45nm Node Include Engineered Substrates”, Solid State Technology, Jul. 2005 Edition, Copyright 2005 by PennWell Corporation, 4 pages.
Smith: “Piezoresistance Effect in Germanium and Silicon”, Physical Review, vol. 94, No. 1, Apr. 1, 1954, pp. 42-49.
Kanda: “A Graphical Representation of the Piezoresistance Coeffcients in Silicon”, IEEE Transactions on Electron Devices, vol. Ed-29, No. 1, 1982 IEEE, pp. 64-70.
King Liu Tsu-Jae
Moroz Victor
Bever Hoffman & Harms LLP
Gurley Lynne A
Harms Jeanette S.
Kearney Naima J
Synopsys Inc.
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