Semiconductor integrated circuit and method of processing...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S233110, C365S233120, C365S233190

Reexamination Certificate

active

07944771

ABSTRACT:
A semiconductor integrated circuit device includes an input unit configured to receive address and command signals, an internal address generator configured to output an internal address signal by adjusting a timing of the input address signal to correspond to a predetermined internal signal processing timing margin, and an internal command generator configured to output an internal command having a predetermined time difference from the internal address signal by adjusting a timing of the input command signal.

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patent: 6484246 (2002-11-01), Tsuchida et al.
patent: 6751157 (2004-06-01), Leung
patent: 7152150 (2006-12-01), Sato et al.
patent: 2009/0154278 (2009-06-01), Chan-Choi et al.
patent: 2001-195895 (2001-07-01), None
patent: 2003-077299 (2003-03-01), None
patent: 1020040095962 (2004-11-01), None
patent: 1020060114737 (2006-11-01), None
patent: 1020070040745 (2007-04-01), None
patent: 100718038 (2007-05-01), None

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