Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle
Reexamination Certificate
2011-07-12
2011-07-12
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
C716S051000, C716S052000, C716S053000, C716S054000, C716S055000
Reexamination Certificate
active
07979811
ABSTRACT:
Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.
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Hung Meg
Tang Hongbo
Wang Xin
Wu Shao-Po
Dinh Paul
Martine & Penilla & Gencarella LLP
Tela Innovations, Inc.
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