System of testing semiconductor devices, a method for...

Classifying – separating – and assorting solids – Sorting special items – and certain methods and apparatus for... – Condition responsive means controls separating means

Reexamination Certificate

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Details

C209S571000, C209S573000, C702S108000

Reexamination Certificate

active

07982155

ABSTRACT:
A system of testing semiconductor devices includes a classification module configured to classify a plurality of lots into a plurality of groups; an apparatus assignment module configured to assign a plurality of testing apparatuses to each of the groups; and a test recipe creation module configured to create a test recipe to test defects in a second group other than a first group specified in the groups, the test recipe including a definition of testing positions in the second group defined by a rule different from the first group.

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Notification of Reasons for Refusal issued by the Japanese Patent Office on Apr. 13, 2010, for Japanese Patent Application No. 2005-075410, and English-language translation thereof.
Asano et al., “Sampling Plan Optimization for CD Control in Low k1Lithography,” Metrology, Inspection, and Process Control for Microlithography XIX, Proc. of SPIE (May 2005), 5752:727-735.
Notification of Reasons for Refusal issued by the Japanese Patent Office on Feb. 15, 2011, for Japanese Patent Application No. 2005-075410, and English-language translation thereof.

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