Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185240, C365S185180, C365S185230, C365S185140, C365S185030

Reexamination Certificate

active

07872919

ABSTRACT:
A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.

REFERENCES:
patent: 2006/0034140 (2006-02-01), Ogawa et al.
patent: 2008/0130366 (2008-06-01), Ueda et al.
patent: 2006-79803 (2006-03-01), None

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