Method and apparatus for scrambling data for control of...

Details Method and apparatus for scrambling data for control of... Method and apparatus for scrambling data for control of...

2011-04-19

2011-04-19

Moe, Aung S (Department: 2474)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S440000, C711S216000, C713S193000, C380S268000

Reexamination Certificate

active

07929549

ABSTRACT:
A memory subsystem includes a master controller that includes a pseudo random bit sequence (PRBS) generator having a plurality of output taps and an exclusive-OR (XOR) unit. The memory subsystem also includes a memory device that is coupled to the master controller via a plurality of single ended bidirectional data paths. The master controller may scramble a plurality of data bits using the PRBS generator and the XOR unit prior to writing the plurality of data bits to the memory device. In addition, the master controller may perform an XOR between each bit of the plurality of data bits and a respective output tap of the PRBS generator prior to conveyance on a respective path of the plurality of single ended bidirectional data paths.

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