Gate array

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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Details

C257S204000, C257S207000, C257S208000, C257S211000

Reexamination Certificate

active

07875909

ABSTRACT:
A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.

REFERENCES:
patent: 5591995 (1997-01-01), Shaw
patent: 5760428 (1998-06-01), Colwell et al.
patent: 5994726 (1999-11-01), Ikeda et al.
patent: 10335613 (1998-12-01), None

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